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Design and Performance Evaluation of the SCAN Secure Processor

Design and Performance Evaluation of the SCAN Secure Processor

Raghudeep Kannavara, Nikolaos Bourbakis
Copyright: © 2015 |Volume: 3 |Issue: 2 |Pages: 24
ISSN: 2166-7241|EISSN: 2166-725X|EISBN13: 9781466680562|DOI: 10.4018/IJMSTR.2015040105
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MLA

Kannavara, Raghudeep, and Nikolaos Bourbakis. "Design and Performance Evaluation of the SCAN Secure Processor." IJMSTR vol.3, no.2 2015: pp.68-91. http://doi.org/10.4018/IJMSTR.2015040105

APA

Kannavara, R. & Bourbakis, N. (2015). Design and Performance Evaluation of the SCAN Secure Processor. International Journal of Monitoring and Surveillance Technologies Research (IJMSTR), 3(2), 68-91. http://doi.org/10.4018/IJMSTR.2015040105

Chicago

Kannavara, Raghudeep, and Nikolaos Bourbakis. "Design and Performance Evaluation of the SCAN Secure Processor," International Journal of Monitoring and Surveillance Technologies Research (IJMSTR) 3, no.2: 68-91. http://doi.org/10.4018/IJMSTR.2015040105

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Abstract

This paper presents the design, performance analysis, security evaluation and the extended instruction set architecture (ISA) of the SCAN secure processor (SCAN-SP). The SCAN-SP is security enhanced SparcV8 processor architecture with an extended ISA to interface with an off-chip FPGA co-processor to handle lossless image compression, encryption and information hiding based on SCAN methodology. Additionally, SCAN-SP offers a SCAN methodology based secure computing feature capable of executing an encrypted instruction stream. Thus the proposed secure processor architecture enables tamper resistant code execution along with cryptographic and general computing capabilities.

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