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Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins

Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins

Vinod Kumar, Ram Murti Rawat
Copyright: © 2021 |Volume: 13 |Issue: 2 |Pages: 13
ISSN: 2643-7937|EISSN: 2643-7945|EISBN13: 9781799863953|DOI: 10.4018/IJSPPC.2021040102
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MLA

Kumar, Vinod, and Ram Murti Rawat. "Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins." IJSPPC vol.13, no.2 2021: pp.16-28. http://doi.org/10.4018/IJSPPC.2021040102

APA

Kumar, V. & Rawat, R. M. (2021). Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins. International Journal of Security and Privacy in Pervasive Computing (IJSPPC), 13(2), 16-28. http://doi.org/10.4018/IJSPPC.2021040102

Chicago

Kumar, Vinod, and Ram Murti Rawat. "Low Power Restoration Circuits Reduce Swing Voltages of SRAM Cell With Improved Read and Write Margins," International Journal of Security and Privacy in Pervasive Computing (IJSPPC) 13, no.2: 16-28. http://doi.org/10.4018/IJSPPC.2021040102

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Abstract

This paper examines the factors that affect the static noise margin (SNM) of static random access memories which focus on optimizing read and write operation of 8T SRAM cell which is better than 6T SRAM cell using swing restoration for dual node voltage. New 8T SRAM technique on the circuit or architecture level is required. In this paper, comparative analysis of 6T and 8T SRAM cells with improved read and write margin is done for 130nm technology with cadence virtuoso schematics tool.

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