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Implementation of FFT on General-Purpose Architectures for FPGA

Implementation of FFT on General-Purpose Architectures for FPGA

Fabio Garzia, Roberto Airoldi, Jari Nurmi
Copyright: © 2010 |Volume: 1 |Issue: 3 |Pages: 20
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781609609672|DOI: 10.4018/jertcs.2010070102
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MLA

Garzia, Fabio, et al. "Implementation of FFT on General-Purpose Architectures for FPGA." IJERTCS vol.1, no.3 2010: pp.24-43. http://doi.org/10.4018/jertcs.2010070102

APA

Garzia, F., Airoldi, R., & Nurmi, J. (2010). Implementation of FFT on General-Purpose Architectures for FPGA. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 1(3), 24-43. http://doi.org/10.4018/jertcs.2010070102

Chicago

Garzia, Fabio, Roberto Airoldi, and Jari Nurmi. "Implementation of FFT on General-Purpose Architectures for FPGA," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 1, no.3: 24-43. http://doi.org/10.4018/jertcs.2010070102

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Abstract

This paper describes two general-purpose architectures targeted to Field Programmable Gate Array (FPGA) implementation. The first architecture is based on the coupling of a coarse-grain reconfigurable array with a general-purpose processor core. The second architecture is a homogeneous multi-processor system-on-chip (MP-SoC). Both architectures have been mapped onto two different Altera FPGA devices, a StratixII and a StratixIV. Although mapping onto the StratixIV results in higher operating frequencies, the capabilities of the device are not fully exploited. The implementation of a FFT on the two platforms shows a considerable speed-up in comparison with a single-processor reference architecture. The speed-up is higher in the reconfigurable solution but the MP-SoC provides an easier programming interface that is completely based on C language. The authors’ approach proves that implementing a programmable architecture on FPGA and then programming it using a high-level software language is a viable alternative to designing a dedicated hardware block with a hardware description language (HDL) and mapping it on FPGA.

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