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Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs

Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs

Simon J. Hollis, Chris Jackson
Copyright: © 2011 |Volume: 2 |Issue: 3 |Pages: 29
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781613506912|DOI: 10.4018/jertcs.2011070102
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MLA

Hollis, Simon J., and Chris Jackson. "Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs." IJERTCS vol.2, no.3 2011: pp.21-49. http://doi.org/10.4018/jertcs.2011070102

APA

Hollis, S. J. & Jackson, C. (2011). Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 2(3), 21-49. http://doi.org/10.4018/jertcs.2011070102

Chicago

Hollis, Simon J., and Chris Jackson. "Implementation and Evaluation of Skip-Links: A Dynamically Reconfiguring Topology for Energy-Efficient NoCs," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 2, no.3: 21-49. http://doi.org/10.4018/jertcs.2011070102

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Abstract

The Skip-link architecture dynamically reconfigures Network-on-Chip (NoC) topologies in order to reduce the overall switching activity in many-core systems. The proposed architecture allows the creation of long-range Skip-links at runtime to reduce the logical distance between frequently communicating nodes. This offers a number of advantages over existing methods of creating optimised topologies already present in research, such as the Reconfigurable NoC (ReNoC) architecture and static Long-Range Link (LRL) insertion. This architecture monitors traffic behaviour and optimises the mesh topology without prior analysis of communications behaviour, and is thus applicable to all applications. The technique described here does not utilise a master node, and each router acts independently. The architecture is thus scalable to future many-core networks. The authors evaluate the performance using a cycle-accurate simulator with synthetic traffic patterns and compare the results to a mesh architecture, demonstrating logical hop count reductions of 12-17%. Coupled with this, up to a doubling in critical load is observed, and the potential for 10% energy reductions on a 16×16 node network.

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