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Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience

Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience

Miloš Krstic, Xin Fan, Eckhard Grass, Luca Benini, M. R. Kakoee, Christoph Heer, Birgit Sanders, Alessandro Strano, Davide Bertozzi
Copyright: © 2012 |Volume: 3 |Issue: 4 |Pages: 18
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781466612020|DOI: 10.4018/jertcs.2012100101
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MLA

Krstic, Miloš, et al. "Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience." IJERTCS vol.3, no.4 2012: pp.1-18. http://doi.org/10.4018/jertcs.2012100101

APA

Krstic, M., Fan, X., Grass, E., Benini, L., Kakoee, M. R., Heer, C., Sanders, B., Strano, A., & Bertozzi, D. (2012). Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 3(4), 1-18. http://doi.org/10.4018/jertcs.2012100101

Chicago

Krstic, Miloš, et al. "Evaluation of GALS Methods in Scaled CMOS Technology: Moonrake Chip Experience," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 3, no.4: 1-18. http://doi.org/10.4018/jertcs.2012100101

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Abstract

In this paper the authors present the concept and evaluation results of a complex GALS ASIC demonstrator in 40 nm CMOS process. This chip, named Moonrake, compares synchronous and GALS synchronization technology in a homogeneous experimental setting: same baseline designs, same manufacturing process, same die. The chip validates GALS technology for both point-to-point and network-centric on-chip communications, demonstrating its potentials for different applications. The design analysis, measurement and test results confirm the potential of GALS approach for the scaled technologies, showing the significant benefits in respect to area, power, and EMI when it comes to the complex system implementation. Furthermore, 91% of the tests performed on the GALS network-on-chip test structures completed successfully, validating the timing robustness of new area and latency-efficient synchronization schemes and proving that the design flow for GALS synchronization technology can be implemented by means of mainstream industrial tools.

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