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Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication

Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication

Prabhat Avasare, Jeroen Declerck, Miguel Glassee, Amir Amin, Erik Umans, Praveen Raghavan, Martin Palkovic
Copyright: © 2013 |Volume: 4 |Issue: 1 |Pages: 22
ISSN: 1947-3176|EISSN: 1947-3184|EISBN13: 9781466631571|DOI: 10.4018/jertcs.2013010103
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MLA

Avasare, Prabhat, et al. "Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication." IJERTCS vol.4, no.1 2013: pp.42-63. http://doi.org/10.4018/jertcs.2013010103

APA

Avasare, P., Declerck, J., Glassee, M., Amin, A., Umans, E., Raghavan, P., & Palkovic, M. (2013). Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 4(1), 42-63. http://doi.org/10.4018/jertcs.2013010103

Chicago

Avasare, Prabhat, et al. "Design Flow for Silicon Chip Implementing Novel Platform Architecture for Wireless Communication," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 4, no.1: 42-63. http://doi.org/10.4018/jertcs.2013010103

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Abstract

In current era of complex chip designs targeting wireless mobile terminals, architects and designers need to conform to tight design constraints – both in terms of performance (e.g. execution time, silicon area, energy consumption) and time-to-market. Further, additional flexibility is required in these designs to handle multiple wireless standards, sometimes even concurrently. To achieve these challenging goals, the authors introduce a platform architecture that uses a decentralized control to minimize communication and control overhead while keeping timing predictable by using state-of-the-art components and a novel interconnect. The authors demonstrate three main achievements in running multiple wireless standards on their platform: 1.053Gbps 4x4 80MHz WLAN 802.11ac receiver data path meeting the SIFS timing with a latency of 12.5µs, dual concurrent 173Mbps 2x2 20MHz Cat-4 3GPP-LTE receiver and platform reconfiguration from WLAN 11n receiver to 3GPP-LTE one in 52µs. Further the authors describe the design flow used to prepare main components of our platform architecture for a tape-out, while especially keeping a close eye on energy consumption. We believe that our chip design flow is generic and can be used in other custom processor chip designs even outside wireless domain.

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