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Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study

Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study

Liang Guang, Ethiopia Nigussie, Juha Plosila, Hannu Tenhunen
Copyright: © 2012 |Volume: 3 |Issue: 3 |Pages: 20
ISSN: 1947-9220|EISSN: 1947-9239|EISBN13: 9781466610514|DOI: 10.4018/jaras.2012070105
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MLA

Guang, Liang, et al. "Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study." IJARAS vol.3, no.3 2012: pp.72-91. http://doi.org/10.4018/jaras.2012070105

APA

Guang, L., Nigussie, E., Plosila, J., & Tenhunen, H. (2012). Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study. International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS), 3(3), 72-91. http://doi.org/10.4018/jaras.2012070105

Chicago

Guang, Liang, et al. "Dual Monitoring Communication for Self-Aware Network-on-Chip: Architecture and Case Study," International Journal of Adaptive, Resilient and Autonomic Systems (IJARAS) 3, no.3: 72-91. http://doi.org/10.4018/jaras.2012070105

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Abstract

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

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