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Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms

Sanna Määttä, Leandro Möller, Leandro Soares Indrusiak, Luciano Ost, Manfred Glesner, Jari Nurmi, Fernando Moraes
Copyright: © 2010 |Volume: 1 |Issue: 1 |Pages: 16
ISSN: 1947-3176|EISSN: 1947-3184|ISSN: 1947-3176|EISBN13: 9781616929817|EISSN: 1947-3184|DOI: 10.4018/jertcs.2010103005
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MLA

Määttä, Sanna, et al. "Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms." IJERTCS vol.1, no.1 2010: pp.86-101. http://doi.org/10.4018/jertcs.2010103005

APA

Määttä, S., Möller, L., Indrusiak, L. S., Ost, L., Glesner, M., Nurmi, J., & Moraes, F. (2010). Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), 1(1), 86-101. http://doi.org/10.4018/jertcs.2010103005

Chicago

Määttä, Sanna, et al. "Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms," International Journal of Embedded and Real-Time Communication Systems (IJERTCS) 1, no.1: 86-101. http://doi.org/10.4018/jertcs.2010103005

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Abstract

Application models are often disregarded during the design of multiprocessor Systems-on-Chip (MPSoC). This is due to the difficulties of capturing the application constraints and applying them to the design space exploration of the platform. In this article we propose an application modelling formalism that supports joint validation of application and platform models. To support designers on the trade-off analysis between accuracy, observability, and validation speed, we show that this approach can handle the successive refinement of platform models at multiple abstraction levels. A case study of the joint validation of a single application successively mapped onto three different platform models demonstrates the applicability of the presented approach.

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