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SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors

SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors

Li Yang, Lu Peng, Balachandran Ramadass
Copyright: © 2008 |Volume: 2 |Issue: 4 |Pages: 13
ISSN: 1930-1650|EISSN: 1930-1669|ISSN: 1930-1650|EISBN13: 9781615203246|EISSN: 1930-1669|DOI: 10.4018/jisp.2008100103
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MLA

Yang, Li, et al. "SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors." IJISP vol.2, no.4 2008: pp.54-66. http://doi.org/10.4018/jisp.2008100103

APA

Yang, L., Peng, L., & Ramadass, B. (2008). SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors. International Journal of Information Security and Privacy (IJISP), 2(4), 54-66. http://doi.org/10.4018/jisp.2008100103

Chicago

Yang, Li, Lu Peng, and Balachandran Ramadass. "SecCMP: Enhancing Critical Secrets Protection in Chip-Multiprocessors," International Journal of Information Security and Privacy (IJISP) 2, no.4: 54-66. http://doi.org/10.4018/jisp.2008100103

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Abstract

Security has been considered as an important issue in processor design. Most of the existing designs of security handling assume the chip as a single secure unit. However, such assumption is vulnerable to exposure resulted from a central failure point. In this article, we propose a secure Chip-Multiprocessor architecture (SecCMP) to handle security related problems such as key protection and core authentication in multi-core systems. Matching the nature of multi-core systems, a distributed threshold secret sharing scheme is employed to protect critical secrets. A critical secret (e.g., encryption key) is divided into multiple shares and distributed among multiple cores instead of being kept a single copy in one core that is sensitive to exposure. The proposed SecCMP can not only enhance the security and fault-tolerance in secret protection but also support core authentication. SecCMP is designed to be an efficient and secure architecture for CMPs.

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