On the Reliability of Post-CMOS and SET Systems

On the Reliability of Post-CMOS and SET Systems

Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici
Copyright: © 2009 |Volume: 1 |Issue: 2 |Pages: 15
ISSN: 1941-6318|EISSN: 1941-6326|ISSN: 1941-6318|EISBN13: 9781615204151|EISSN: 1941-6326|DOI: 10.4018/jnmc.2009040103
Cite Article Cite Article

MLA

Stanisavljevic, Milos, et al. "On the Reliability of Post-CMOS and SET Systems." IJNMC vol.1, no.2 2009: pp.43-57. http://doi.org/10.4018/jnmc.2009040103

APA

Stanisavljevic, M., Schmid, A., & Leblebici, Y. (2009). On the Reliability of Post-CMOS and SET Systems. International Journal of Nanotechnology and Molecular Computation (IJNMC), 1(2), 43-57. http://doi.org/10.4018/jnmc.2009040103

Chicago

Stanisavljevic, Milos, Alexandre Schmid, and Yusuf Leblebici. "On the Reliability of Post-CMOS and SET Systems," International Journal of Nanotechnology and Molecular Computation (IJNMC) 1, no.2: 43-57. http://doi.org/10.4018/jnmc.2009040103

Export Reference

Mendeley
Favorite Full-Issue Download

Abstract

The necessity of applying fault-tolerant techniques to increase the reliability of future nano-electronic systems is an undisputed fact, dictated by the high density of faults that will plague these chips. The averaging and thresholding fault-tolerant technique that has proven remarkable efficiency in CMOS is presented for SET-based designs. Computer simulations demonstrate the superiority of this fault-tolerant technique over other methods, which is specifically the case when an adaptable threshold is used.

Request Access

You do not own this content. Please login to recommend this title to your institution's librarian or purchase it from the IGI Global bookstore.