Estimating the Worst-Case Execution Time of the Shared Data Cache in Integrated CPU-GPU Architectures

Yijie Huangfu; Wei Zhang

doi:10.5626/JCSE.2018.12.4.139

주제분류

...

저널정보

한국정보과학회
Journal of Computing Science and Engineering 학술저널
Journal of Computing Science and Engineering Vol.12 No.4
2018.12 139 - 148 (10page)
DOI : 10.5626/JCSE.2018.12.4.139

저자정보

Yijie Huangfu (Virginia Commonwealth University)
Wei Zhang (Virginia Commonwealth University)

이용수
내서재: 0

내서재에 추가
되었습니다. 내서재에서
삭제되었습니다.

초록·키워드

오류제보하기

Integrated CPU-GPU architectures have the potential to increase performance and energy efficiency for a variety of applications, due to their tight coupling of the CPU and GPU cores. However, in order to serve hard real-time and safetycritical applications, the integrated CPU-GPU architecture must be time-predictable and worst-case execution time (WCET) analyzable. In this work, we study the shared data last-level cache (LLC) in the integrated CPU-GPU architecture and propose an access interval-based method in order to estimate the worst-case cache misses of the LLC. The results indicate that the proposed technique can effectively improve the accuracy of the miss rate estimation in the LLC. We also find that the improved LLC miss rate estimations can be used to further improve the WCET estimations of the GPU kernels running on the integrated CPU-GPU architecture.

#Graphics Processing Units (GPUs) #Worst-Case Execution Time (WCET) #Cache memories #Integrated CPU-GPU