Abstract
On-chip communication design includes designing software parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware parts (on-chip communica-tackle two problemunication interfaces of processor/IP/memory, etc.). For an efficient tion network, commign space, we need fast scheduling and timing analysis. In this work, we exploration of its dess. One is to incorporate the dynamic behavior of software (interrupt processing and context switching) into on-chip communication scheduling. The other is to reduce on-chip data storage required for on-chip communication, by making different communications to share a physical communication buffer. To solve the problems, we present both integer linear programming formulation and heuristic algorithm.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
J Brunel, W. Kruijtzer, H. Kenter, F. Petrot, L. Pasquier, and E. Kock. “COSY Communication IP’s.” In Proceedings of Design Automation Conference, pp. 406–409, 2000.
W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. Jerayya, and M. Diaz-Nava. “Component-based Design Approach for Multicore SoCs.” In Proceedings of Design Automation Conference, June 2002.
Jon Kleinsmith and Daniel D. Gajski. “Communication Synthesis for Reuse.” UC Irvine, Technical Report ICS-TR-98-06, February 1998.
T. Yen and W. Wolf. “Communication Synthesis for Distributed Embedded Systems.” In Proceedings of ICCAD, 1995.
R. B. Ortega and G. Borriello. “Communication Synthesis for Distributed Embedded Systems.” In Proceedings of ICCAD, 1998.
M. Gasteier and M. Glesner. “Bus-Based Communication Synthesis on System-Level.” ACM Transactions on Design Automation of Electronic Systems, Vol. 4, No. 1, 1999.
K. Lahiri, A. Raghunathan, and S. Dey. “System-Level Performance Analysis for Designing On-Chip Communication Architecture.” In IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, June 2001.
P. Knudsen and J. Madsen. “Integrating Communication Protocol Selection with Hardware/Software Codesign.” In IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, August 1999.
ARM, Inc. AMBA™ Specification (Rev 2.0), available in http://www.arm.com/.
Sonics Inc., “Sonics Integration Architecture,” available in http://www.sonicsinc.com/.
W. J. Dally and B. Towles. “Route Packet, Not Wires: On-Chip Interconnection Networks.” In Proceedings of Design Automation Conference, June 2001.
A. Siebenborn, O. Bringmann, and W. Rosenstiel. “Worst-Case Performance of Parallel, Communicating Software Processes.” In Proceedings of CODES 2002, 2002.
Cadence Inc., VCC available at http://www.cadence.com.
Amer Baghdadi, Nacer-Eddine Zergainoh, Wander O. Cesário, and Ahmed Amine Jerraya, “Combining a Performance Estimation Methodology with a Hardware/Software Codesign Flow Supporting Multiprocessor Systems.” IEEE Transactions on Software Engineering, Vol. 28, No. 9, pp. 822–831, September 2002.
Redhat Inc., eCos, available in http://www.redhat.com/embedded/technologies/ecos/.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Kluwer Academic Publishers
About this chapter
Cite this chapter
Cho, Y., Lee, G., Choi, K., Yoo, S., Zergainoh, NE. (2003). Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design. In: Jerraya, A.A., Yoo, S., Verkest, D., Wehn, N. (eds) Embedded Software for SoC. Springer, Boston, MA. https://doi.org/10.1007/0-306-48709-8_10
Download citation
DOI: https://doi.org/10.1007/0-306-48709-8_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7528-5
Online ISBN: 978-0-306-48709-5
eBook Packages: Springer Book Archive