Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation

Abstract

Instruction Reuse (IR) is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an optimizing compiler, they do not succeed many a time due to limited knowledge of run-time data. In this article we concentrate on integer ALU and load instructions in packet processing applications and see how IR can be used to obtain better performance. In addition, we attempt to answer the following questions in the article - (1) Can IR be improved by reducing interference in the reuse buffer?, (2) What characteristics of network applications can be exploited to improve IR?, and (3) What is the effect of IR on resource contention and memory accesses? We propose an aggregation scheme that combines the high-level concept of network traffic i.e. “flows” with the low level microarchitectural feature of programs i.e. repetition of instructions and data and propose an architecture that exploits temporal locality in incoming packet data to improve IR by reducing interference in the RB. We find that the benefits that can be achieved by exploiting IR varies widely depending on the nature of the application and input data. For the benchmarks considered, we find that IR varies between 1% and 50% while the speedup achieved varies between 1% and 24%.