Abstract
This chapter presents a problem in conventional methods of validating software design for NoC: software validation at different abstraction levels. As a solution to resolve the problem, a method of multi-level software validation is explained.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
W. Cesario, A. Baghdadi, L. Gauthier, D. Lyonnard, G. Nicolescu, Y. Paviot, S. Yoo, A. A. Jerraya, and M. Diaz-Nava, Component-Based Design Approach for Multicore SoCs, Proc. Design Automation Conference, June 2002.
M. Diaz-Nava and G.S. Okvist, “The Zipper Prototype: A Complete and Flexible VDSL Multi-carrier Solution,” ST Microelectronics, J. of System Research, vol. 2, no. 1, Oct. 2001.
P. Guerrier and A. Greiner, “A Generic Architecture for On-Chip Packet-Switched Interconnection,” Proc. Design Automation and Test in Europe, 2000.
J. A. J. Leiten, et. al, “Stream Communication between Real-Time Tasks in a High Performance Multiprocessor,” Proc. Design Automation and Test in Europe, 1998.
B. Mukherjee, K. Schwan, Prabha Gopinath, “A Survey of Multiprocessor Operating System Kernels”, Technical Report GIT-CC-92/05, College of Computing, Georgia Institute of Technology, Nov. 1993.
D. Wingard, “Micronetwork-Based Integration for SOCs,” Proc. Design Automation Conference, pp. 673–677, 2001.
H. Takada, “μITRON: A Standard Real-Time Kernel Specification for Small-Scale Embedded Systems”, Real-Time Magazine, 1997, q3.
L. Lindh, et. al., “Hardware Accelerator for Single and Multiprocessor Real-Time Operating Systems”, Proc. Seventh Swedish Workshop on Computer System Architecture, June, 1998.
J. Lee, K. Ryu and V. Mooney, “A Framework for Automatic Generation of Configuration Files for a Custom Hardware/Software RTOS,” Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA’02), pp. 31–37, June 2002.
Validation in a Component-Based Design Flow for Multicore SoCs, G. Nicolescu, S. Yoo, A. Boucchima and A. A. Jerraya, Proc. International Symposium on System Synthesis, Oct. 2002.
James A. Rowson, “Hardware/Software Co-Simulation”, Proc. Design Automation Conference, 1994.
L. Semeria and A. Ghosh, “Methodology for Hardware/Software Coverification in C/C++”, Proc. Asia South Pacific Design Automation Conference, 2000.
S. M. Tan, et. al., “Virtual Hardware for Operating System Development”, Technical rep., UIUC, Sep. 1995, available at http://choices.cs.uiuc.edu/uChoices/Papers/uChoices/vchoices/vchoices.pdf
D. Desmet,. et. al, “Operating System Based Software Generation for Systems-on-Chip”, Proc. Design Automation Conference, 2000.
Carbon Kernel, available at http://www.carbonkernel.org/
M. Lajolo, M. Lazarescu, A. Sangiovanni-Vincentelli, “A Compilation-based Software Estimation Scheme for Hardware/Software Co-simulation”, Proc. International Symposium on Hardware/Software Co-design, 1999.
J. Cockx, “Efficient Modeling of Preemption in a Virtual Prototype”, Proc. IEEE International Workshop on Rapid System Prototyping, June 2000.
M. Bradley and K. Xie, Hardware/Software Co-Verification with RTOS Application Code, Mentor Graphics Inc. available at http://www.mentor.com/soc/fulfiUment/mentorpaper_10280.pdf
S. Yoo, et. al, “Fast Prototyping of an IS-95 CDMA Cellular Phone: a Case Study”, Proc. Asia Pacific Chip Design Languages, Oct. 1999.
P. Gerin, S. Yoo, G. Nicolescu and A. A. Jerraya, “Scalable and Flexible Cosimulation of SoC Designs with Heterogeneous Multi-Processor Target Architectures”, Proc. Asia South Pacific Design Automation Conference, 2001.
S. Yoo, G. Nicolescu, L. Gauthier and A. A. Jerraya, “Automatic Generation of Fast Timed Simulation Models for OS in SoC Design”, Proc. Design Automation and Test in Europe, Mar. 2002.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Kluwer Academic Publishers
About this chapter
Cite this chapter
Yoo, S., Nicolescu, G., Bacivarov, I., Youssef, W., Bouchhima, A., Jerraya, A.A. (2003). Multi-Level Software Validation for NoC. In: Jantsch, A., Tenhunen, H. (eds) Networks on Chip. Springer, Boston, MA. https://doi.org/10.1007/0-306-48727-6_13
Download citation
DOI: https://doi.org/10.1007/0-306-48727-6_13
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-7392-2
Online ISBN: 978-0-306-48727-9
eBook Packages: Springer Book Archive