Abstract
This chapter introduces morphware as the basis of a second machine paradigm, which mainly has been introduced by the discipline of embedded system design, targeting the system on chip (SoC). But more recently SoC design is adopting more and more computer science (CS) mentality and also needs the services of computer science (CS) professionals. CS is going to include the morphware paradigm in its intellectual infrastructure. The time has come to bridge the traditional hardware-software chasm. A dichotomy of two machine paradigms is the road map to upgrade CS curricula by evolution, rather than by revolution. This chapter mainly introduces morphware platforms as well as their models and architectures.
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References
http://www.darpa.mil/ipto/programs/pca/vision.htm
http://morphware.net/
A. Burks, H. Goldstein, J. von Neumann (1946): Preliminary discussion of the logical design of an electronic computing instrument. US Army Ordnance Department Report.
H. Goldstein, J. von Neumann, and A. Burks (1947): Report on the mathematical and logical aspects of an electronic computing instrument. Princeton Institute of Advanced Study.
D. Jansen et al. (2003): The electronic design automation handbook, Kluwer.
P. Gillick (2003): State of the art FPGA development tools. Reconfigurable Computing Workshop, Orsay, France.
M. J. Smith (1997): Application specific integrated circuits, Addison Wesley.
D. Chinnery and K. Keutzer (2002): Closing the gap between ASIC & custom, Kluwer.
R. Hartenstein (invited paper) (1987): The Microprocessor is no more general purpose Proc. IEEE International Symposium on Innovative Systems (ISIS), Austin, Texas.
T. Makimoto (keynote) (2000): The rising wave of field-programmability, Proc. FPL 2000, Villach, Austria, August 27–30, Springer-Verlag, Heidelberg/New York.
F. Faggin, M. Hoff, S. Mazor, and M. Shima (1996): The history of 4004. IEEE Micro. Dec. 1996.
J. Becker (invited tutorial) (2003): Reconfigurable computing systems. Proceedings Escola de Microelectrônica da SBC-Sul (EMICRO 2003). Rio Grande, Brasil, September.
B. Lewis (2002): Gartner Dataquest, October 28.
P. Athanas (1992): An adaptive Machine Architecture and Compiler for Dynamic Processor Reconfiguration Ph.D thesis, Brown University, Providence, Rhode Island.
S. Vassiliadis, S. Wong, and S. Cotofana (2001): The MOLEN rm-coded processor. Proc. FPL.
M. Iliopoulos, T. Antonakopoulos (2000): Reconfigurable network processors based on field-programmable system level integrates circuits. Proc. FPL.
http://www.fccm.org
R. Hartenstein (1995): Custom computing machines. DMM’95, Smolenice, Slovakia.
http://www.springer.de/comp/lncs/
http://fpl.org
S. Hauck (1998): The role of FPGAs in reprogrammable systems. Proc. IEEE.
V. Betz, J. Rose, and A. Marquardt (eds.) (1999): Architecture and CAD for deep-submicron FPGas. Kluwer.
S. Hoffmann (2003): Modern FPGAs, reconfigurable platforms and their design tools. Proc. REASON summer school. Ljubljana, Slovenia, August 11–13.
D. Soudris et al. (2002): Survey of existing fine grain reconfigurable hardware platforms. Deliverable D9 AMDREL consortium (Architectures and Methodologies for Dynamically Reconfigurable Logic).
J. Oldfield and R. Dorf (1995): Field-programmable gate arrays: Reconfigurable logic for rapid prototyping and implementation of digital systems. Wiley-Interscience.
http://www.xilinx.com
http://www.altera.com
V. George and J. Rabaey (2001): Low-energy FPGAs: Architecture and design. Kluwer.
Z. Salcic and A. Smailagic (1997): Digital systems design and prototyping using field programmable logic. Kluwer.
J. Hamblen and M. Furman (2001): Rapid prototyping of digital systems. Kluwer.
R. Männer and R. Spurzem et al. (1999): AHA-GRAPE: Adaptive hydrodynamic architecture-GRAvity PipE. Proc. FPL.
G. Lienhart (2003): Beschleunigung hydrodynamischer N-Körper-simulationen mit rekonfigurierbaren rechensystemen. Joint 33rd Speedup and 19th PARS Workshop. Basel, Switzerland, March 19–21.
N. Ebisuzaki et al. (1997): Astrophysical Journal, 480, 432.
T. Narumi, R. Susukita, H. Furusawa, and T. Ebisuzaki (2000): 46 Tflops Special-purpose computer for molecular dynamics simulations WINE-2. Proc. 5th Int’l Conf. on Signal Processing. Beijing 575–582.
T. Narumi, R. Susukita, T. Koishi, K. Yasuoka, H. Furusawa, A. Kawai, and T. Ebisuzaki (2000): 1.34 Tflops molecular dynamics simulation for NaCl with a special-purpose computer: MDM. SC2000, Dallas.
T. Narumi, A. Kawai, and T. Koishi (2001): An 8.61 Tflop/s molecular dynamics simulation for NaCl with a special-purpose computer: MDM. SC2001, Denver.
T. Narumi, R. Susukita, T. Ebisuzaki, G. McNiven, and B. Elmegreen (1999): Molecular dynamics machine: Special-purpose computer for molecular dynamics simulations. Molecular Simulation, 21, 401–415.
T. Narumi (1998): Special-Purpose Computer for Molecular Dynamics Simulations Ph D dissertation, University of Tokyo.
T. Thurner (2003): Trends in der automobile-elektronik; GI/ITG FG AH-Zielplan-Workshop at FDL 2003. Frankfurt /Main, Germany.
T. Kean (invited keynote) (2000): It’s FPL, Jim-but not as we know it! Market opportunities for the New commercial architectures. Proc. FPL.
R. Zeidman (2002): Designing with FPGAs and CPLDs. CMP Books.
U. Meyer-Baese (2001): Digital signal processing with field programmable gate arrays (With CD-ROM). Springer-Verlag.
K. Coffman (1999): Real World FPGA design with verilog. Prentice Hall.
R. Seals and G. Whapshott (1997): Programmable logic: PLDs and FPGAs. McGraw-Hill.
G. Martin and H. Chang (ed.) (2003): Winning the SoC revolution: Experiences in real design. Kluwer.
G. Ou and M. Potkonjak (2003): Intellectual property protection in VLSI design. Kluwer.
P. J. Ashenden (2001): The designer’s guide to VHDL (2nd Ed.), Morgan Kaufmann.
http://www.mentor.com/fpga/
http://www.synplicity.com/
http://www.celoxica.com/
http://www.dac.com
http://www.mathworks.com/products/connections/product_main.shtml?prod_id=304
http://www.celoxica.com/methodology/matlab.asp
http://www.mathworks.com/
I. Jones (2003): DARPA funded Directions in embedded computing. Reconfigurable Computing Workshop. Orsay, France, Sept.
T. Grötker et al. (2002): System design with system-C. Kluwer.
http://www.synopsys.com/products/concentric_systemC/cocentric_systemC_ds.html
http://www.systemc.org/
http://www.synopsys.com/
J. Hoe, Arvind: Hardware synthesis from term rewriting systems. Proc. VLSI’99. Lisbon, Portugal.
M. Ayala-Rincón et al. (2003): Efficient computation of algebraic operations over dynamically reconfigurable systems specified by rewriting-logic environments. Proc. 23rd SCCC. IEEE CS press.
M. Ayala-Rincón et al. (2003): Architectural specification, exploration and simulation through rewriting-logic. Colombian J. Comput. 3(2), 20–34.
M. Ayala-Rincón et al. (2003): Using rewriting-logic notation for functional verification in data-stream-based reconfigurable computing. Proc. FDL 2003 (Forum on Specification and Design Languages). Frankfurt /Main, Germany, September 23–26.
P. Bjureus et al. (2002): FPGA Resource and timing estimation from mat-lab execution traces 10th Int’l Workshop on Hardware/Software Codesign. Estes Park, Colorado, May 6–8.
V. Baumgarten, G. Ehlers, F. May, A. Nückel, M. Vorbach, and M. Weinhardt (2003): PACT XPP-A self-reconfigurable data processing architecture. The J. Supercomputing. 26(2), Sept. 2003, 167–184.
J. Rabaey (1997): Reconfigurable processing: The solution to low-power programmable DSP. Proc. ICASSP.
http://public.itrs.net/Files/2002Update/2002Update.htm
N. N., Department of Trade and Industry (DTI), London, UK, 2001
H. Simmler et al. (2000): Multitasking on FPGA coprocessors. Proc. FPL
H. Walder and M. Platzner (2003): Reconfigurable hardware operating systems: From design concepts to realizations. Proc. ERSA 2003.
H. Walder and M. Platzner (2004): A runtime environment for reconfigurable hardware operating systems. Proc. FPL 2004.
R. Hartenstein (invited paper) (2002): Reconfigurable computing: Urging a revision of basic CS curricula. Proc. 15th Int’l Conf. on Systems Engineering (ICSENG02). Las Vegas, USA, 6–8 Aug. 2002.
course ID=27 in: http://vlsil.engr.utk.edu/~bouldin/COURSES/HTML/courselist.html
C. Stroud et al. (2002): BIST-based diagnosis of FPGA interconnect. Proc. IEEE Int’l. Test Conf.
P. Zipf (2002): A Fault Tolerance Technique for Field-Programmable Logic Arrays Dissertation. Univ. Siegen, Germany.
http.//directreadout.gsfc.nasa.gov
M. Abramovici and C, Stroud (2000): Improved BIST-based diagnosis of FPGA logic blocks. Proc. IEEE Int’l Test Conf.
http://www.xilinx.com/events/docs/esc_sf2001_microblaze.pdf
http://www.leox.org/
J. Becker and M. Vorbach (2003): An industrial/academic configurable system-on-chip project (CSoC): Coarse.grain XPP/Leon-based architecture integration. DATE.
http://www.gaisler.com/leonmain.html
C. Mead and L. Conway (1980): Introduction to VLSI systems design. Addison-Wesley.
R. Kress et al.: A datapath synthesis system (DPSS) for the reconfigurable datapath architecture. Proc. ASP-DAC’95
http://pactcorp.com
V. Baumgarten et al. (2001): PACT XPP-A self-reconfigurable data processing architecture. ERSA.
J. Becker, A. Thomas, M. Vorbach, and G. Ehlers (2002): Dynamically reconfigurable systems-on-chip: A core-based industrial/academic SoC synthesis project. IEEE Workshop Heterogeneous Reconfigurable SoC. Hamburg, Germany, April 2002.
J. Cardoso and M. Weinhardt (2003): From C programs to the configure-execute model. DATE.
R. Hartenstein (2001): A decade of research on reconfigurable architectures. DATE.
W. Mangione-Smith et al. (1997): Current issues in configurable computing research. IEEE Computer, Dec 1997.
J. Becker, T. Pionteck, and M. Glesner (2000): An application-tailored dynamically reconfigurable hardware architecture for digital baseband processing. SBCCI.
M. Sauer (2003): Issues in concept development for embedded wireless SoCs. GI/ITG FG AH-Zielplan-Workshop. Frankfurt /Main, Germany.
A. Wiesler, F. Jondral (2002): A software radio for second and third generation mobile systems. IEEE Trans. on Vehicular Technology. 51,(4), July.
N. Petkov (1992): Systolic parallel processing. North-Holland.
M. Foster, H. Kung (1980): Design of special-purpose VLSI chips: Example and opinions. ISCA.
H. T. Kung (1982): Why systolic architectures? IEEE Computer 15(1), 37–46
http://directreadout.gsfc.nasa.gov
U. Nageldinger et al. (2000): Generation of design suggestions for coarsegrain reconfigurable architectures FPL 2000.
U. Nageldinger (2001): Coarse-grained Reconfigurable Architectures Design Space exploration Dissertation,-downloadable from [99]
http://xputers.informatik.uni-kl.de/papers/publications/NageldingerDiss.html
J. Frigo et al. (2001): Evaluation of the streams-C C-to-FPGA compiler: An applications perspective. FPGA.
T.J. Callahan: Instruction-level parallelism for reconfigurable computing. FPL’98
E. Caspi et al. (2000): Extended version of: Stream computations organized for reconfigurable execution (SCORE). FPL’2000.
T. Callahan (2000): Adapting software pipelining for reconfigurable computing. CASES
H. Kwok-Hay So, BEE (2000): A Reconfigurable Emulation Engine for Digital Signal Processing Hardware M.S. thesis, UC Berkeley.
C. Chang, K. Kuusilinna, R. Broderson (2002): The biggascale emulation engine. FPGA.
B. Mei et al. (2003): Exploiting loop-level parallelism on coarse-grained reconfigurable architectures using modulo scheduling. DATE 2003.
M. Herz et al. (invited paper) (2002): Memory organization for data-stream-based reconfigurable computing ICECS.
M. Herz et al. (1997): A novel sequencer hardware for application specific computing. Proc. ASAP.
H. Reinig et al. (1995): Novel sequencer hardware for high-speed signal processing. Proc. Design Methodologies for Microelectronics, Smolenice, Slovakia.
M. Herz (2001): High Performance Memory Communication Architectures for Coarse-grained Reconfigurable Computing Systems Ph.D. thesis, Kaiserslautern-downloadable from: [111]
http://xputers.informatik.uni-kl.de/papers/publications/HerzDiss.html
F. Catthoor et al. (2002): Data access and storage management for embedded programmable processors. Kluwer.
F. Catthoor et al. (1998): Custom memory management methodology exploration of memory organization for embedded multimedia systems design. Kluwer.
M. Weber et al. (1988): MOM-map oriented machine. In (E. Chiricozzi, A. D’Amico (ed.) Parallel Processing and Applications. North-Holland.
A. Hirschbiel et al. (1987): A flexible architecture for image processing. Microprocessing and Microprogramming. 21, 65–72.
A. Ast et al. (1994): Data-procedural languages for FPL-based machines. FPL’94.
E. Mirsky and A. DeHon (1996): MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources. Proc. IEEE FCCM’96. April 17–19 Napa, CA, USA.
E. Waingold et al. (1997): Baring it all to software: RAW machines. IEEE Computer. 86–93.
J. Becker et al. (2000): Architecture and application of a dynamically reconfigurable hardware array for future mobile communication systems. Proc. FCCM’00. April 17–19, Napa, CA, USA.
C. Ebeling et al. (1996): RaPiD: Reconfigurable pipelined datapath. Proc. FPL’96.
S. C. Goldstein et al. (1999): PipeRench: A coprocessor for streaming multimedia acceleration. Proc. ISCA’99, May 2–4 Atlanta.
D. Chen and J. Rabaey (1990): PADDI: Programmable arithmetic devices for digital signal processing. VLSI Signal Processing IV, IEEE Press.
D. C. Chen and J. M. Rabaey (1992): A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths. IEEE J. Solid-State Circuits. 27(12).
A. K. W. Yeung and J. M. Rabaey (1993): A reconfigurable data-driven multiprocessor architecture for rapid prototyping of high throughput DSP algorithms. Proc. HICSS-26. Jan. Kauai, Hawaii.
N. Tredennick (1995): Technology and business: Forces driving microprocessor evolution. Dec. Proc. IEEE.
J. Becker et al. (1998): Parallelization in co-compilation for configurable accelerators. Proc. ASP-DAC’98.
J. Becker (1997): A partitioning compiler for computers with Xputer-based Accelerators Ph.D. Dissertation, University of Kaiserslautern. downloadable from [128].
http://xputers.informatik.uni-kl.de/papers/publications/BeckerDiss.pdf
L. Lamport (1974): The parallel execution of Do-loops. C. ACM 17,2, Feb.
D. Loveman (1977): Program improvement by source-to-source transformation. J. ACM 24,1.
W. Abu-Sufah, D. Kuck, and D. Lawrie (1981): On the performance enhancement of paging systems through program analysis and transformations. IEEE-Trans. C-30(5).
U. Banerjee (1979): Speed-up of ordinary programs; Ph.D. Thesis, University of Illinois at Urbana-Champaign, Oct. DCS Report No. UIUCDCS-R-79-989.
J. Allen, K. Kennedy (1984): Automatic loop interchange. Proc. ACM SIG-PLAN’84, Symp. on Compiler Construction, Montreal, Canada, SIGPLAN Notices June 19, 6.
J. Becker and K. Schmid (1998): Automatic parallelism exploitation for FPL-based accelerators. Hawaii Int’l. Conf. on System Sciences (HICSS’98), Big Island, Hawaii.
http://xputers.informatik.uni-kl.de/staff/hartenstein/eishistory_en.html
D. Knapp et al. (1991): The ADAM design planning engine. IEEE Trans CAD.
J. Lopez et al. (1992): Design assistance for CAD frameworks. Proc. EURODAC’92. Hamburg, Sept. 7–10, Germany.
L. Guerra et al. (1998): A methodology for guided behavioral level optimization. Proc. DAC’98, June 15–19, San Francisco.
C. A. Moritz et al. (1999): Hot Pages: software caching for RAW microprocessors. MIT. LCS-TM-599, Aug. Cambridge, MA.
P.-A. Hsiung et al. (1999): PSM: An object-oriented synthesis approach to multiprocessor design. IEEE Trans VLSI Systems 4/1. March.
J. Kin et al. (1999): Power efficient media processor design space exploration. Proc. DAC’99. June 21–25, New Orleans, http://anti-machine.org.
K. Schmidt et al. (1990): A novel ASIC design approach based on a new machine paradigm. J. SSC-invited reprint from Proc. ESSCIRC.
W. Nebel et al. (1984): PISA, a CAD package and special hardware for pixel-oriented layout analysis. ICCAD.
R. Hartenstein et al. (1990): A novel paradigm of parallel computation and its use to implement simple high performance hardware. Future Generation Computer Systems 791/92,-invited reprint fr. Proc. InfoJapan’90 (Int’l Conf. Commemorating the 30th Anniversary Computer Society of Japan), Tokyo, Japan.
C. Chang et al. (2001): The biggascale emulation engine (Bee). summer retreat UC Berkeley.
D. Gajski et al. (1982): A second opinion on dataflow machines. Computer, Feb.
J. Backus (1978): Can programming be liberated from the von Neumann style? A functional style and its algebra of programs. Communications of the ACM, August, 20(8), 613–641.
J. Rabaey (keynote) (2000): Silicon Platforms for the Next Generation Wireless Systems. Proc. FPL.
G. Koch et al. (1975): The universal bus considered harmful. Proc. 1st EUROMICRO Symposium on the microarchitecture of computing systems. Nice, France, North Holland.
J. Dongarra, I. Foster, G. Fox, W. Gropp, K. Kennedy, L. Torczon, and A. White (ed.) (2002): The sourcebook of parallel computing. Morgan Kaufmann.
Arvind et al. (1983): A Critique of Multiprocessing the von Neumann Style. Proc. ISCA.
G. Bell (keynote) (2000): All the chips outside. The architecture challenge. Proc. ISCA.
G. Amdahl (1967): Validity of the single processor approach to achieving large-scale computing capabilities. AFIPS Conference Proceedings. (30).
J. Hennessy (1999): ISCA25: Looking backward, looking forward. Proc. ISCA.
http://www.ece.lsu.edu/vaidy/raw04/
http://xputers.informatik.uni-kl.de/raw/index_raw.html
http://www.iti.uni-luebeck.de/PARS/
http://www.speedup.ch/
http://www.hoise.com/primeur/03/articles/monthly/AE-PR-04-03-61.html
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Hartenstein, R. (2006). Morphware and Configware. In: Zomaya, A.Y. (eds) Handbook of Nature-Inspired and Innovative Computing. Springer, Boston, MA. https://doi.org/10.1007/0-387-27705-6_11
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