Abstract
Today’s System on Chip (SoC) technology can achieve unprecedented computing speed that is shifting the IC design bottleneck from computation capacity to communication bandwidth and flexibility. This chapter presents an innovative methodology for automatically generating the energy models of a versatile and parametric on-chip communication IP (STBus). Eventually, those models are linked to a standard SystemC simulator, running at BCA and TLM abstraction level. To make the system power simulation fast and effective, we enhanced the STBus class library with a new set of power profiling features (“Power API”), allowing performing power analysis either statically (i.e.: total avg. power) or at simulation runtime (i.e.: dynamic profiling). In addition to random patterns, our methodology has been extensively benchmarked with the high-level SystemC simulation of a real world multi-processor platform (MPARM). It consists of four ARM7TDMI processors accessing a number of peripheral targets (including several banks of SRAMs, Interrupt’s slaves and ROMs) through the STBus communication infrastructure. The power analysis of the benchmark platform proves to be effective and highly correlated, with an average error of 2% and a RMS of 0.015 mW vs. the reference (i.e. gate level) power figures. The chapter ends presenting a new and effective methodology to minimize the Design of Experiments (DoE) needed to characterize the above power models. The experimental figures show that our DoE optimization techniques are able to trade off power modeling approximation with characterization cost, leading to a 60% average reduction of the sampling space, with 20% of maximum error.
STMicroelectronics
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks: an Engineering Approach”, IEEE Computer Society Press, 1997.
K. Lahiri, S. Dey et al.,“Efficient Exploration of the SOC Communication Architecture Design Space”, Proc. of ICCAD-2000, Nov. 2000, S.Jose’, USA.
W. Dally, B. Toles, “Route Packets, not Wires: On-Chip Interconnection Network”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.
A. Sangiovanni Vincentelli, J. Rabaey, K. Keutzer et al., “Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.
F. Karim, A. Nguyen et al., “On Chip Communication Architecture for OC-768 Network Processors”, Proceedings of 38th DAC 2001, June 2001, Las Vegas, USA.
K. Lahiri, S. Dey et al.,“Evaluation of the Traffic Performance Characteristics of System-on-Chip Communication Architectures”, Proc. 14th Int’l Conference on VLSI Design 2001, Los Alamitos, USA.
L. Benini, G. De Micheli, “Network on Chip: A New SoC Paradigm”, IEEE Computer, January 2002.
T. Ye, L. Benini, G. De Micheli, “Analysis of power consumption on switch fabrics in network routers”, Proceedings of 39th DAC 2002, June 2002, New Orleans, USA.
S. Kumar et al., “A network on chip architecture and design methodology”, Intemational Symposium on VLSI 2002.
H.-S. Wang, X. Zhu, L.-S. Peh, and S. Malik, “Orion: A Power-Performance Simulator for Interconnection Networks”, International Symposium on Microarchitecture, MICRO-35, November 2002, Istanbul, Turkey.
T. Ye, G. De Micheli and L. Benini, “Packetized On-Chip Interconnect Communication Analysis for MPSoC”, Proceedings of DATE-03, March 2003, Munich, Germany, pp. 344–349.
J. Hu and R. Marculescu, “Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures”, Proceedings of DATE-03, March 2003, Munich, Germany, pp. 688–693.
T. Grotker, S. Liao, G. Martin and S. Swan, “System Design with SystemC”, Kluwer Academic Publishers, 2002.
“STBus Communication System: Concepts and Definitions”, Reference Guide, STMicroelectronics, October 2002.
“STBus Functional Specs”, STMicroelectronics, public web support site, http://www.stmcu.com/inchtml-pages-STBus_intro.html, STMicroelectronics, April 2003.
Synopsys Inc., “Core Consultant Reference Manual”, “Power Compiler Reference Manual” and “VCS: Verilog Compiled Simulator Reference Manual”, v2003.06, June 2003.
C. Patel, S. Chai, S. Yalamanchili, and D. Schimmel, “Power-constrained design of multiprocessor interconnection networks,” in Proc. Int. Conf. Computer Design, pp. 408–416, Oct. 1997.
H. Zimmermann, “OSI Reference Model — The ISO model of architecture for Open System Interconnection”, IEEE Trans. on Communication, n 4, April 1980.
VSI Alliance Standard, “System-Level Interface Behavioral Documentation Standard Version 1”, Released March 2000.
Box, George E. P. and Draper Norman Richard. Empirical model-building and response surfaces, John Wiley & Sons New York, 1987
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer Science + Business Media, Inc.
About this chapter
Cite this chapter
Bona, A., Zaccaria, V., Zafalon, R. (2004). System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip. In: Macii, E. (eds) Ultra Low-Power Electronics and Design. Springer, Boston, MA. https://doi.org/10.1007/1-4020-8076-X_13
Download citation
DOI: https://doi.org/10.1007/1-4020-8076-X_13
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-8075-3
Online ISBN: 978-1-4020-8076-0
eBook Packages: Springer Book Archive