Abstract
In vector processors, when several vector streams concurrently access the memory system, references of different vectors can interfere in the access to the memory modules, causing module conflicts. Besides, in a memory system where several modules are mapped in every bus, delays due to bus conflicts are added to module conflict delays. This paper proposes an access order to the vector elements that avoids conflicts when the concurrent access corresponds to vectors of a subfamily, and the request rate to the memory modules is less than or equal to the service rate. For other cases of concurrent access, the proposal dramatically reduces conflicts.
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del Corral, A.M., Llaberia, J.M. (1999). New Access Order to Reduce Inter-Vector Conflicts. In: Hernández, V., Palma, J.M.L.M., Dongarra, J.J. (eds) Vector and Parallel Processing – VECPAR’98. VECPAR 1998. Lecture Notes in Computer Science, vol 1573. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10703040_32
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DOI: https://doi.org/10.1007/10703040_32
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