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Formal Specification and Verification of ARM6

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Theorem Proving in Higher Order Logics (TPHOLs 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2758))

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Abstract

This paper gives an overview of progress made on the formal specification and verification of the ARM6 micro-architecture using the HOL proof system. The ARM6 is a commercial processor design prevalent in mobile and embedded systems – it features a 3-stage pipeline with a multi-cycle execute stage, six operating modes and a rich 32-bit RISC instruction set. This paper describes some of the difficulties encountered when working with a full blown instruction set architecture that has not been designed with verification in mind.

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References

  1. Aagaard, M.D., Cook, B., Day, N.A., Jones, R.B.: A framework for microprocessor correctness statements. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 433–448. Springer, Heidelberg (2001)

    Chapter  Google Scholar 

  2. Barras, B.: Programming and computing in HOL. In: Aagaard, M.D., Harrison, J. (eds.) TPHOLs 2000. LNCS, vol. 1869, pp. 17–37. Springer, Heidelberg (2000)

    Chapter  Google Scholar 

  3. Berezin, S., Clarke, E., Biere, A., Zhu, Y.: Verification of out-of-order processor designs using model checking and a light-weight completion function. Formal Methods in System Design 20(2), 187–222 (2002)

    Article  Google Scholar 

  4. Birtwistle, G., Subrahmanyam, P.A. (eds.): VLSI Specification, Verification and Synthesis. Kluwer Academic Publishers, Dordrecht (1988)

    MATH  Google Scholar 

  5. Brock, B., Kaufmann, M., Moore, J.S.: ACL2 theorems about commercial microprocessors. In: Srivas, M., Camilleri, A. (eds.) FMCAD 1996. LNCS, vol. 1166, pp. 275–293. Springer, Heidelberg (1996)

    Chapter  Google Scholar 

  6. Cohn, A.: The notion of proof in hardware verification. Journal of Automated Reasoning 5(2), 127–139 (1989)

    Article  MATH  Google Scholar 

  7. Fox, A.C.J.: Algebraic Models for Advanced Microprocessors. PhD thesis, University of Wales Swansea (1998)

    Google Scholar 

  8. Fox, A.C.J.: An algebraic framework for modelling and verifying microprocessors using HOL. Technical Report 512, University of Cambridge, Computer Laboratory (April 2001)

    Google Scholar 

  9. Fox, A.C.J.: A HOL specification of the ARM instruction set architecture. Technical Report 545, University of Cambridge, Computer Laboratory (June 2001)

    Google Scholar 

  10. Fox, A.C.J.: Formal verification of the ARM6 micro-architecture. Technical Report 548, University of Cambridge, Computer Laboratory (November 2002)

    Google Scholar 

  11. Graham, B.T.: The SECD Microprocessor, A Verification Case Study. Kluwer International Series in Engineering and Computer Science. Kluwer Academic Publishers, Dordrecht (1992)

    MATH  Google Scholar 

  12. Harman, N.A., Tucker, J.V.: Algebraic models and the correctness of microprocessors. In: Milne, G.J., Pierre, L. (eds.) CHARME 1993. LNCS, vol. 683, pp. 92–108. Springer, Heidelberg (1993)

    Chapter  Google Scholar 

  13. Hunt Jr., W.A.: FM8501: A Verified Microprocessor. LNCS, vol. 795. Springer, Heidelberg (1994)

    MATH  Google Scholar 

  14. Hunt Jr., W.A., Brock, B.C.: A formal HDL and its use in the FM9001 verification. In: Hoare, C.A.R., Gordon, M.J.C. (eds.) Mechanized Reasoning and Hardware Design, pp. 35–47. Prentice-Hall, Englewood Cliffs (1992)

    Google Scholar 

  15. Jones, R.B., Skakkebæk, J.U., Dill, D.L.: Formal verification of out-of-order execution with incremental flushing. Formal Methods in System Design 20(2), 139–158 (2002)

    Article  MATH  Google Scholar 

  16. Joyce, J.J.: Formal verification and implementation of a microprocessor. In: Birtwistle and Subrahmanyam [4], pp. 129–157

    Google Scholar 

  17. Kaufmann, M., Manolios, P., Moore, J.S. (eds.): Computer-Aided Reasoning: ACL2 Case Studies. Kluwer Academic Publishers, Dordrecht (2000)

    Google Scholar 

  18. McMillan, K.: Verification of an implementation of tomasulo’s algorithm by compositional model checking. In: Hu, A.J., Vardi, M.Y. (eds.) CAV 1998. LNCS, vol. 1427. Springer, Heidelberg (1998)

    Chapter  Google Scholar 

  19. Melham, T.F.: Abstraction mechanisms for hardware verification. In: Birtwistle and Subrahmanyam [4], pp. 267–291

    Google Scholar 

  20. Miller, S.P., Srivas, M.K.: Applying formal verification to the AAMP5 microprocessor: A case study in the industrial use of formal methods. Formal Methods in Systems Design 8(2), 153–188 (1996)

    Article  Google Scholar 

  21. Sawada, J., Hunt Jr., W.A.: Verification of FM9801: An out-of-order model with speculative execution, exceptions, and program-modifying capability. Formal Methods in System Design 20(2), 187–222 (2002)

    Article  MATH  Google Scholar 

  22. Seal, D. (ed.): ARM Architectural Reference Manual, 2nd edn. Addison-Wesley, Reading (2001)

    Google Scholar 

  23. Tahar, S., Kumar, R.: A practical methodology for the formal verification of RISC processors. Formal Methods in System Design 13(2), 159–225 (2002)

    Article  Google Scholar 

  24. Tomasulo, R.M.: An efficient algorithm for exploiting multiple arithmetic units. IBM Journal 11(34), 25–33 (1967)

    Article  MATH  Google Scholar 

  25. Windley, P.J., Coe, M.L.: A correctness model for pipelined microprocessors. In: Kumar, R., Kropf, T. (eds.) TPCD 1994. LNCS, vol. 901, pp. 33–51. Springer, Heidelberg (1995)

    Google Scholar 

  26. Wong, W.: Modelling bit vectors in HOL: The word library. In: Joyce, J.J., Seger, C.-J.H. (eds.) HUG 1993. LNCS, vol. 780, pp. 371–384. Springer, Heidelberg (1994)

    Google Scholar 

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Authors and Affiliations

  1. University of Cambridge, Cambridge

    Anthony Fox

Authors
  1. Anthony Fox
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Editor information

Editors and Affiliations

  1. Information Security Group, Dep. of Computer Science, ETH Zurich, Switzerland

    David Basin

  2. Computer Science Dept., Saarland University, 66123, Saarbrücken, Germany

    Burkhart Wolff

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Fox, A. (2003). Formal Specification and Verification of ARM6. In: Basin, D., Wolff, B. (eds) Theorem Proving in Higher Order Logics. TPHOLs 2003. Lecture Notes in Computer Science, vol 2758. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10930755_2

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  • DOI: https://doi.org/10.1007/10930755_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40664-8

  • Online ISBN: 978-3-540-45130-3

  • eBook Packages: Springer Book Archive

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