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Formal Specification and Verification of ARM6

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Theorem Proving in Higher Order Logics (TPHOLs 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2758))

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Abstract

This paper gives an overview of progress made on the formal specification and verification of the ARM6 micro-architecture using the HOL proof system. The ARM6 is a commercial processor design prevalent in mobile and embedded systems – it features a 3-stage pipeline with a multi-cycle execute stage, six operating modes and a rich 32-bit RISC instruction set. This paper describes some of the difficulties encountered when working with a full blown instruction set architecture that has not been designed with verification in mind.

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Authors and Affiliations

  1. University of Cambridge, Cambridge

    Anthony Fox

Authors
  1. Anthony Fox
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Editor information

Editors and Affiliations

  1. Information Security Group, Dep. of Computer Science, ETH Zurich, Switzerland

    David Basin

  2. Computer Science Dept., Saarland University, 66123, Saarbrücken, Germany

    Burkhart Wolff

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© 2003 Springer-Verlag Berlin Heidelberg

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Fox, A. (2003). Formal Specification and Verification of ARM6. In: Basin, D., Wolff, B. (eds) Theorem Proving in Higher Order Logics. TPHOLs 2003. Lecture Notes in Computer Science, vol 2758. Springer, Berlin, Heidelberg. https://doi.org/10.1007/10930755_2

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  • DOI: https://doi.org/10.1007/10930755_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40664-8

  • Online ISBN: 978-3-540-45130-3

  • eBook Packages: Springer Book Archive

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