A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures

Abstract

Field Programmable Gate Arrays (FPGAs) are being used as platforms for the digital implementation of intelligent systems. Binary digital systems provide an accurate, robust, stable performance that is free from the drift and manufacturing tolerances associated with analogue systems. However binary systems have a much lower functional density than their analogue counterparts resulting in inefficient use of silicon surface area. A design for a novel Configurable Logic Block (CLB) is presented which retains the robust qualities of digital processing whilst providing increased functional density. The circuit design uses Si/SiGe Inter-band Tunneling Diodes (ITDs) and NMOS/CMOS transistors to create quaternary memory cells in a topology and architecture suited to the implementation of neural networks. The performance of the CLB is simulated in HSPICE and the results are presented.