Abstract
In this paper, we focus on engineering Pareto–optimal digital circuits given the expected input/output behaviour with a minimal design effort. The design objectives to be minimised are: hardware area, response time and power consumption. We do so using the Strength Pareto Evolutionary Algorithms. The performance and the quality of the circuit evolved for some benchmarks are presented then compared to those of single objective genetic algorithms as well as to the circuits obtained by human designers.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Zitzler, E., Thiele, L.: Multi0objective evolutionary algorithms: a comparative case study and the strength Pareto approach. IEEE Transactions on Evolutionary Computation 3(4), 257–271 (1999)
Ercegovac, M.D., Lang, T., Moreno, J.H.: Introduction to digital systems. John Wiley, Chichester (1999)
Hsiao, M.S.: Peak power estimation using genetic spot optimization for large VLSI circuits. In: Proc. European Conference on Design, Automation and Test, March 1999, pp. 175–179 (1999)
Najm, F.N.: A survey of power estimation techniques in VLSI circuits. IEEE Transactions on VLSI Systems 2(4), 446–455 (1994)
Coello, C.A.: A short tutorial on evolutionary multi-objective optimisation. In: Proc. First Conference on Evolutionary Multi-Criterion Optimisation (2001)
Edgeworth, F.Y.: Mathematical psychics: an essay on the application of mathematics to the moral sciences. In: Kelley, A.M. (ed.), New York (1967)
Pareto, V.: Cours d’économie politique, volume I, II, F. Rouge, Lausanne (1896)
Rosenman, M.A., Gero, J.S.: Reducing the Pareto set in multi-criterion optimisation. Engineering Optimisation 8(3), 189–206 (1985)
Horn, J., Nafpliotis, N., Goldber, D.: A niched Pareto genetic algorithm for multi-objective optimisation. In: Proc. IEEE Conference on Evolutionary Computation, IEEE World Congress on Computational Intelligence, vol. 1, pp. 82–87 (1994)
Nedjah, N., Mourelle, L.M.: A comparison of two circuit representations for evolutionary digital circuit design. In: Orchard, B., Yang, C., Ali, M. (eds.) IEA/AIE 2004. LNCS, vol. 3029, pp. 351–360. Springer, Heidelberg (2004)
Coelho, A., Christiansen, A., Aguirre, A.: Towards automated evolutionary design of combinational circuits. Comput. Electr. Eng. 27, 1–28 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Nedjah, N., de Macedo Mourelle, L. (2005). Pareto-Optimal Hardware for Digital Circuits Using SPEA. In: Ali, M., Esposito, F. (eds) Innovations in Applied Artificial Intelligence. IEA/AIE 2005. Lecture Notes in Computer Science(), vol 3533. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11504894_72
Download citation
DOI: https://doi.org/10.1007/11504894_72
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26551-1
Online ISBN: 978-3-540-31893-4
eBook Packages: Computer ScienceComputer Science (R0)