Skip to main content

First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption

  • Conference paper
Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3553))

Included in the following conference series:

Abstract

Microarchitects should consider energy consumption, together with performance, when designing instruction cache architecture, especially in embedded processors. This paper proposes a power-aware instruction cache architecture, named Partitioned Instruction Cache (PI-Cache), to reduce dynamic energy consumption in the instruction cache. The proposed PI-Cache is composed of several small sub-caches. When the PI-Cache is accessed, only one sub-cache is accessed by utilizing the locality of applications. In the meantime, the other sub-caches are not accessed, resulting in dynamic energy reduction. The PI-Cache also reduces energy consumption by eliminating energy consumed in tag matching. Moreover, performance loss is little, considering the physical cache access time. We evaluated the energy efficiency by running cycle accurate simulator, SimpleScalar, with power parameters obtained from CACTI. Simulation results show that the PI-Cache reduces dynamic energy consumption by 42% – 59%.

This work was supported by the Brain Korea 21 Project.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Segars, S.: Low power design techniques for microprocessors. In: Proceedings of International Solid-State Circuits Conference (2001)

    Google Scholar 

  2. Kin, J., Gupta, M., Mangione-Smith, W.: The filter cache: An energy efficient memory structure. In: Proceedings of International Symposium on Microarchitecture, pp. 184–193 (1997)

    Google Scholar 

  3. Bellas, N., Hajj, I., Polychronopoulos, C.: Using dynamic cache management techniques to reduce energy in a high-performance processor. In: Proceedings of International Symposium on Low Power Electronics and Design, pp. 64–69 (1999)

    Google Scholar 

  4. Albonesi, D.H.: Selective cache ways: On-demand cache resource allocation. In: Proceedings of International Symposium on Microarchitecture, pp. 70–75 (1999)

    Google Scholar 

  5. Powell, M., Agarwal, A., Vijaykumar, T.N., Falsafi, B., Roy, K.: Reducing set-associative cache energy via way-prediction and selective direct-mapping. In: Proceedings of International Symposium on Microarchitecture, pp. 54–65 (2001)

    Google Scholar 

  6. Montanaro, J., et al.: A 160 Mhz, 32b, 0.5W CMOS RISC microprocessor. In: Proceedings of International Solid-State Circuits Conference, pp. 214–229 (1996)

    Google Scholar 

  7. Lee, C., Potkonjak, M., Mangione-Smith, W.: A tool for evaluating and synthesizing multimedia and communications systems. In: Proceedings of the 30th Annual International Symposium on Microarchitecture, pp. 330–335 (1997)

    Google Scholar 

  8. SPEC CPU2000 Benchmarks, http://www.specbench.org

  9. Kim, S., Vijaykrishnan, N., Kandemir, M., Sivasubramaniam, A., Irwin, M.J.: Partitioned instruction cache architecture for energy efficiency. ACM Transactions on Embedded Computing Systems 2, 163–185 (2003)

    Article  Google Scholar 

  10. Chang, Y.-J., Lai, F., Ruan, S.-J.: Cache design for eliminating the address translation bottleneck and reducing the tag area cost. In: Proceedings of International Conference on Computer Design 334 (2002)

    Google Scholar 

  11. ARM Corp.: ARM1136J(F)-S, available at http://www.arm.com/products/CPUs/ARM1136JF-S.html

  12. Burger, D., Austin, T.M., Bennett, S.: Evaluating future micro-processors: The SimpleScalar tool set. Technical Report TR-1308, Univ. of Wisconsin-Madison Computer Sciences Dept. (1997)

    Google Scholar 

  13. Shivakumar, P., Jouppi, N.P.: CACTI 3.0: An integrated cache timing, power, and area model. TR-WRL-2001-2 (2001)

    Google Scholar 

  14. Muller, M.: At the Heart of Innovation, available at http://www.arm.com/miscPDFs/6871.pdf

  15. Samsung Electronics: ASIC STD130 DATABOOK (2001)

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Kim, C.H., Shim, S., Kwak, J.W., Chung, S.W., Jhon, C.S. (2005). First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_12

Download citation

  • DOI: https://doi.org/10.1007/11512622_12

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-26969-4

  • Online ISBN: 978-3-540-31664-0

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics