Abstract
It takes more than a good tool to shorten the time-to-market window: the scalability of a design also plays an important role in rapid prototyping if it needs to satisfy various demands. The design of JPEG2000 belongs to such cases. As the latest compression standard for still images, JPEG2000 is well tuned for diverse applications, raising different throughput requirements on its composed blocks. In this paper, a scalable embedded JPEG2000 encoder architecture is presented and prototyped onto Xilinx FPGA. The system level design presents dynamic profiling outcomes, proving the necessity of the design for scalability.
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© 2005 Springer-Verlag Berlin Heidelberg
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Zhang, C., Long, Y., Kurdahi, F. (2005). A Scalable Embedded JPEG2000 Architecture. In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2005. Lecture Notes in Computer Science, vol 3553. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11512622_36
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DOI: https://doi.org/10.1007/11512622_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26969-4
Online ISBN: 978-3-540-31664-0
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