Abstract
Computer systems usually rely on hardware counters and software instrumentation to acquire performance information about the cache access behavior. These approaches either provide only limited data or are restricted in their applicability. This paper introduces a novel approach based on a hardware cache monitoring facility that exhibits both the details of traditional software mechanisms and the low–overhead of hardware counters. More specially, the cache monitor can be combined with any location of the memory hierarchy and present a detailed view of the complete memory access behavior of applications. The monitoring concept has been verified using a multiprocessor simulator. Initial experimental results show its feasibility in terms of hardware design and functionality with respect to providing comprehensive performance data.
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Tao, J., Jeitner, J., Trinitis, C., Karl, W., Weidendorfer, J. (2005). Comprehensive Cache Inspection with Hardware Monitors. In: Malyshkin, V. (eds) Parallel Computing Technologies. PaCT 2005. Lecture Notes in Computer Science, vol 3606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535294_29
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DOI: https://doi.org/10.1007/11535294_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28126-9
Online ISBN: 978-3-540-31826-2
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