Abstract
Testing of a fabricated chip is a process that applies a sequence of inputs to the chip and analyzes the chip’s output sequence to ascertain whether it functions correctly. As the chip density grows to beyond millions of gates, Embedded systems and systems-on-chip testing becomes a formidable task. Vast amounts of time and money have been invested by the industry just to ensure the high testability of products. On the other hand, as design complexity drastically increases, current gate-level design and test methodology alone can no longer satisfy stringent time-to-market requirements. The High-Level Test Synthesis (HLTS) system, which this paper mainly focuses on, is to develop new systematic techniques to integrate testability consideration, specially the Built-In Self-Test (BIST) methodology, into the synthesis process. It makes possible for an automatic synthesis tool to predict testability of the synthesized embedded systems or chips accurately in the early stage. It also optimizes the designs in terms of test cost as well as performance and hardware area cost.
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Yang, L.T., Muzio, J. (2005). Testing Methodologies for Embedded Systems and Systems-on-Chip. In: Wu, Z., Chen, C., Guo, M., Bu, J. (eds) Embedded Software and Systems. ICESS 2004. Lecture Notes in Computer Science, vol 3605. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535409_3
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DOI: https://doi.org/10.1007/11535409_3
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