Abstract
The advent of FPGAs and Intellectual Property core availability allow great freedom in the customization of platform processors for embedded systems. One of the new challenges that such technologies present is how to implement a high performance application on devices with hundreds coarse-grained computing units running at 200 MHz, rather than on one processor running at 20 GHz. Consequently, to profit by spatial parallelism that such devices offer becomes a non marginal issue. From the architectural point of view, at least two questions arise: how to exploit such spatial parallelism; how to program such platforms. The first one brings us to seriously reconsider the dataflow paradigm, given the fine grain nature of its operations. The second one brings us to seriously reconsider the functional programming style, given its inherent simplicity in writing parallel programs. In this paper we will discuss our experience in combining these two approaches inside CODACS (COnfigurable DAtaflow Computing System) demonstrator. The resulting architecture offers interesting properties not only as stand-alone computing system but also as development tool for Application Specific Processor (ASPs) prototyping activities.
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Verdoscia, L. (2005). CODACS Project: A Development Tool for Embedded System Prototyping. In: Wu, Z., Chen, C., Guo, M., Bu, J. (eds) Embedded Software and Systems. ICESS 2004. Lecture Notes in Computer Science, vol 3605. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11535409_8
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DOI: https://doi.org/10.1007/11535409_8
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