Using Model-Based Test Program Generator for Simulation Validation

Abstract

The continuous advances in microelectronics design are creating a significant challenge to design validation in general. Tackling pipelined microprocessors is remarkably more demanding. This paper presents a methodology to automatically produce a test program for simulation-based validation of microprocessors maximizing the given verification constraints. The approach integrates an accurate c-simulator to trace internal states, including memory access patterns, cache states, pipeline states and so on, of the target processor to generate test vectors with higher efficiency. The test program generator is integrated into a co-verification environment, which is used to verify an embedded processor with a 7-statge pipeline developed by our team and gained remarkable effects.