Abstract
The need for high precision calculations in various scientific disciplines has led to development of systems with various solutions specific to the problem on hand. The complexity of such systems not withstanding, a generic solution could be the use of neural networks. To be able to leverage the best out of the neural network, hardware implementations are ideal as they give speed-up of several orders of magnitude over software simulations. A simple architecture for such a neuro-chip is proposed in this paper. The neuro-chip supports the current draft version of the IEEE-754 standard for floating-point arithmetic. The synthesis results indicate an estimated 84 MCUPS speed of operation.
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Kala, K.L., Srinivas, M.B. (2005). A 32-Bit Binary Floating Point Neuro-Chip. In: Wang, L., Chen, K., Ong, Y.S. (eds) Advances in Natural Computation. ICNC 2005. Lecture Notes in Computer Science, vol 3612. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11539902_130
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DOI: https://doi.org/10.1007/11539902_130
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28320-1
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