Abstract
Spike-timing dependent synaptic plasticity (STDP) circuitry is designed in 0.35μm CMOS VLSI. By setting different circuit parameters and generating diverse spike inputs, we got different steady weight distributions. Through analysing these simulation results, we show the effect of membrane threshold and input rate in STDP adaptation.
An erratum to this chapter can be found at http://dx.doi.org/10.1007/11550907_163 .
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Huo, J., Murray, A. (2005). The Role of Membrane Threshold and Rate in STDP Silicon Neuron Circuit Simulation. In: Duch, W., Kacprzyk, J., Oja, E., Zadrożny, S. (eds) Artificial Neural Networks: Formal Models and Their Applications – ICANN 2005. ICANN 2005. Lecture Notes in Computer Science, vol 3697. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11550907_159
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DOI: https://doi.org/10.1007/11550907_159
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