Abstract
The proposed work includes CMOS design of a Neuron to generate binary logic Artificial Neural Network (ANN) as well as Multilayer Neural network. Several neural net chips exist on the market today. Some of these chips operate as analog devices by running below threshold on the transistors thereby gaining continuous properties instead of discrete properties afforded by CMOS transistor logic. In the current paper, authors have proposed a weighter circuit. It is designed with the help of NAND & XOR gates & binary connections are stored in flops. Both the gates provide more flexibility than the way the neuron deals with the input. Two-phase clocking with no overlap is used to ensure that all weights are properly shifted in without any data corruption. The same concept is extended to multilayer network.
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© 2005 Springer-Verlag Berlin Heidelberg
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Deshmukh, A., Morghade, J., Khera, A., Bajaj, P. (2005). Binary Neural Networks – A CMOS Design Approach. In: Khosla, R., Howlett, R.J., Jain, L.C. (eds) Knowledge-Based Intelligent Information and Engineering Systems. KES 2005. Lecture Notes in Computer Science(), vol 3681. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11552413_184
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DOI: https://doi.org/10.1007/11552413_184
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-28894-7
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