Abstract
Embedded devices designed for various real-time multimedia and telecom applications, have a bottleneck in energy consumption and performance that becomes day by day more crucial. This is imposed by the increasing gap between processor and memory speed. Many authors have addressed this problem, but all existing techniques either consider only performance without any other trade-off, or they operate at the level of individual loops. We fill this gap, by presenting a technique which achieves parallelization in the memory accesses through four loop transformations. Our estimations from two real-life applications from the multimedia and telecom domain, reveal that using our technique, we can either increase the performance (up to 35%) or lower the energy consumption (up to 20%) for the same cost.
This work was partially sponsored by a scholarship from Public Benefit Foundation of Alexander S. Onasis and from Marie Curie Host Fellowship project HPMT-CT-2000-00031
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Dasygenis, M., Brockmeyer, E., Catthoor, F., Soudris, D., Thanailakis, A. (2005). Improving the Memory Bandwidth Utilization Using Loop Transformations. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_13
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DOI: https://doi.org/10.1007/11556930_13
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