Abstract
An integer quadratic programming based formulation is proposed for the design of FIR filters implemented on Digital Signal Processors (DSP). The method unifies the cost of switching activity and number of ones in coefficients and is applicable to DSPs having multiple multiply accumulate units. Four FIR filter examples are designed with the proposed method. Power simulation results show that up to 38% power reduction can be achieved in the multiply accumulate unit of a DSP using the optimized coefficients. The resulting coefficients show better performance than coefficients optimized with previously proposed methods such as reordering coefficients.
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© 2005 Springer-Verlag Berlin Heidelberg
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Aktan, M., Dündar, G. (2005). Design of Digital Filters for Low Power Applications Using Integer Quadratic Programming. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_15
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DOI: https://doi.org/10.1007/11556930_15
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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