Abstract
In this paper, we propose a novel Interconnect Driver circuit scheme for on-chip bus structures, which changes it’s drive strength based on the switching pattern of the neighbouring interconnect. The circuit is quite simple compared to driver circuits proposed in the literature. The results show that for the cost of a few transistors, the proposed driver circuit has a wider eye opening (upto a 100% improvement) and reduced jitter (up to a 32% reduction) than a traditional driver for typical DSM technologies.
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© 2005 Springer-Verlag Berlin Heidelberg
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Weerasekera, R., Zheng, LR., Pamunuwa, D., Tenhunen, H. (2005). Switching Sensitive Driver Circuit to Combat Dynamic Delay in On-Chip Buses. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_29
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DOI: https://doi.org/10.1007/11556930_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
Online ISBN: 978-3-540-32080-7
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