Abstract
CMOS buffers driving high capacitive loads play an important role in determining the overall performances of present-day complex integrated circuits. Ad hoc optimisation techniques require effective models simple enough to enable the optimisation of multi-million gate circuits.
However, due to size and supply voltage reduction, the behaviour of deep-sub micron devices may differ significantly from the conventional one and the classical models and techniques need to be improved or radically modified. In the paper the Authors show how the well-exploited assumption of a linear relationship between the channel width and the current meanly conducted during the switching transient may be incorrect for deep-submicron buffer transistors. As direct consequence, it follows that the common practice of widening the channel width of the MOSFET transistors may not lead to the expected results in terms of buffer output resistance reduction.
On these bases, a novel expression to estimate the actual effect of a channel widening on the output resistance of CMOS buffer that agrees with HSPICE circuit simulations within 3% error is presented.
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Cappuccino, G., Pugliese, A., Cocorullo, G. (2005). Output Resistance Scaling Model for Deep-Submicron Cmos Buffers for Timing Performance Optimisation. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_34
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DOI: https://doi.org/10.1007/11556930_34
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29013-1
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