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Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2005)

Abstract

In this paper, we present a model, Internode, that unifies the gate functional behavior and the dynamic one. It is based on a FSM that represents the internal state of the gate depending on the electrical load of its internal nodes allowing to consider aspects like input collisions and internal power consumption. Also, we explain the importance of internal power consumption (such effect occurs when an input transition does not affect the output) in three different technologies (AMS 0.6 μm, AMS 0.35 μm, and UMC 130 nm). This consumption becomes more remarkable as technology advances yielding to underestimating up to 9.4% of global power consumption in the UMC 130 nm case. Finally, we show how to optimize power estimation in the SCMOS NOR-2 gate by applying Internode to modeling its consumption accurately.

This work has been partially supported by the MEC META project TEC 2004-00840/MIC of the Spanish Government

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Millán Calderón, A. et al. (2005). Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_35

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  • DOI: https://doi.org/10.1007/11556930_35

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29013-1

  • Online ISBN: 978-3-540-32080-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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