Abstract
Reducing leakage current in memories is critical for low-power designs in deep submicron technology. A common architectural technique consists of lowering the supply voltage to operate SRAM cells in sub-threshold (V th ). This paper investigates stability aspects of sub-V th SRAM cells, both analytically and by simulation in STMicroelectronics’ 90nm CMOS technology. For the first time analytical expressions for the Static Noise Margin in sub-V th as a function of circuit parameters, operating conditions and process variations are derived. The 3G receiver case study illustrates the leakage saving potential of stable sub-V th SRAM designs resulting into energy savings of up to 65%.
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Wellig, A., Zory, J. (2005). Static Noise Margin Analysis of Sub-threshold SRAM Cells in Deep Sub-micron Technology. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_50
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DOI: https://doi.org/10.1007/11556930_50
Publisher Name: Springer, Berlin, Heidelberg
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