Abstract
This paper presents an approach for power-aware code exploration, through an analysis mechanism based on Coloured Petri Net (CPN). Given a code under interest and a CPN description of architecture, a CPN model of application (processor + code) is generated. Coloured Petri Net models allow the application of widespread analysis approaches, for instance simulation and/or state-space exploration. Additionally, this work presents a framework where a widespread CPN tool is applied to processor architecture description, model validation and analysis by simulation. A Petri net integration environment was extended in order to support specific power-aware analysis. In the present approach, such framework is focused on the Embedded Systems context, covering pipeline-less and simplescalar architectures.
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Junior, M.N.O. et al. (2005). A Retargetable Environment for Power-Aware Code Evaluation: An Approach Based on Coloured Petri Net. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_6
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DOI: https://doi.org/10.1007/11556930_6
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