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Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3728))

Abstract

In this work, the optimization of circuits design by using multiobjective evolutionary algorithm is addressed. This methodology enable to deal with circuit specifications -formulated as objective functions- that can be conflicting and want to be optimize at the same time. After the optimization process, a set of different trade-off solutions for the design of the circuit is obtained. This way, SPEA (Strength Pareto Evolutionary Algorithm) has been tested as optimizer of an hybrid CBL/CMOS configurable cell. As a result, some conclusions about the optimized values of the transistor sizes of this cell in order to minimized some power comsumption and delay timing specifications are obtained.

This work has been partially sponsored by UHU2004-06 project

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Author information

Authors and Affiliations

  1. Dept. Teoría de la Señal, Telemática y Comunicaciones, Universidad de Granada,  

    Francisco de Toro

  2. Dept. Ing. Electrónica de Sist. Informáticos y Automática, Universidad de Huelva,  

    Raúl Jiménez & Manuel Sánchez

  3. Dept. Arquitectura y Tecnología de Computadores, Universidad de Granada,  

    Julio Ortega

Authors
  1. Francisco de Toro
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  2. Raúl Jiménez
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  3. Manuel Sánchez
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  4. Julio Ortega
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Editor information

Editors and Affiliations

  1. Electrical and Computer Engineering Department, University of Patras, Greece

    Vassilis Paliouras

  2. IMEC, Kapeldreef 75, 3001, Heverlee, Belgium

    Johan Vounckx

  3. Dept. of Electrical Engineering, VUB, Brussels, Belgium

    Diederik Verkest

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© 2005 Springer-Verlag Berlin Heidelberg

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de Toro, F., Jiménez, R., Sánchez, M., Ortega, J. (2005). Synthesis of Hybrid CBL/CMOS Cell Using Multiobjective Evolutionary Algorithms. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_64

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  • DOI: https://doi.org/10.1007/11556930_64

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29013-1

  • Online ISBN: 978-3-540-32080-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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