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A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers

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Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3728))

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Abstract

A new method for predicting timing jitter caused by device noise in current-mode logic (CML) frequency dividers is presented. Device noise transformation into jitter is modeled as a linear time-varying (LTV) process, as opposed to a previously published method, which models jitter generation as a linear time-invariant (LTI) process. Predictions obtained using the LTV method match jitter values obtained through exhaustive simulation with an error of up to 7.7 %, whereas errors of the jitter predicted by the LTI method exceed 57 %.

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© 2005 Springer-Verlag Berlin Heidelberg

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Aleksic, M., Nedovic, N., Current, K.W., Oklobdzija, V.G. (2005). A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency Dividers. In: Paliouras, V., Vounckx, J., Verkest, D. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2005. Lecture Notes in Computer Science, vol 3728. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11556930_74

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  • DOI: https://doi.org/10.1007/11556930_74

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29013-1

  • Online ISBN: 978-3-540-32080-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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