DLV (Deep Low Voltage): Circuits and Devices

Abstract

There will be a lot of different approaches to achieve the low power on a given system. Multiple modest speed processors will provide the better power-performance product compared to that of a high speed single one. Application dependent memory partitioning and non-blocking memory subsystem will make it possible to reduce unoptimized bus switching power including low power cache design. One of the most efficient way to reduce the power is going to implement the lowest operating voltage circuits as low as possible. The power equation below 130nm process is as follows: Power = afCV ² + bV ³ + cV ⁵. The a term can be decided from architectural features such as swithing efficiency. The b term is from subthreshold leakage and the c term from gate leakage. If we operate 1GHz processor at 0.1V compared to that of current 1V, then power reduction can be 1/100 for a term, 1/1,000 for b term, and 1/100,000 for c term. We will explore how low the operating voltage would be possible in the CMOS circuits and devices, and we will discuss the barriers and challenges to achieve the DLV for ultra low power design.