Abstract
This paper proposes efficient techniques to reconfigure a multi-processor array, which embedded in a 6-port switch lattice in the form of a rectangular grid. It has been shown that the proposed architecture with 6-port switches eliminate gate delays and notably increase the harvest when compared with one using 4-port switches. A new rerouting algorithm combines the latest techniques to maximize harvest without increase in reconfiguration time. Experimental results show that the new reconfiguration algorithm consistently outperforms the most efficient algorithm proposed in literature.
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References
Horita, T., Takanami, I.: Fault-tolerant processor arrays based on the 1.5-track switches with flexible spare distributions. IEEE Trans. on Computers 49(6), 542–552 (2000)
Kuo, S.Y., Chen, I.Y.: Efficient reconfiguration algorithms for degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design 11(10), 1289–1300 (1992)
Low, C.P., Leong, H.W.: On the reconfiguration of degradable VLSI/WSI arrays. IEEE Trans. Computer-Aided Design of integrated circuits and systems 16(10), 1213–1221 (1997)
Low, C.P.: An efficient reconfiguration algorithm for degradable VLSI/WSI arrays. IEEE Trans. on Computers 49(6), 553–559 (2000)
Jigang, W., Srikanthan, T.: An Improved Reconfiguration Algorithm for Degradable VLSI arrays. Journal of Systems Architecture 49, 23–31 (2003)
Fukushi, M., Horiguchi, S.: Self-Reconfigurable Mesh Array System on FPGA. In: Proc. of IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 240–248 (2000)
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© 2005 Springer-Verlag Berlin Heidelberg
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Jigang, W., Srikanthan, T., Heiko, S. (2005). Efficient Techniques and Hardware Analysis for Mesh-Connected Processors. In: Hobbs, M., Goscinski, A.M., Zhou, W. (eds) Distributed and Parallel Computing. ICA3PP 2005. Lecture Notes in Computer Science, vol 3719. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11564621_52
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DOI: https://doi.org/10.1007/11564621_52
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29235-7
Online ISBN: 978-3-540-32071-5
eBook Packages: Computer ScienceComputer Science (R0)