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Random Stimuli Generation for Functional Hardware Verification as a CP Application

  • Conference paper
Principles and Practice of Constraint Programming - CP 2005 (CP 2005)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 3709))

Abstract

Functional verification of modern hardware design consumes roughly 70% of the effort invested in the design cycle. Simulation of randomly generated stimuli is the main means of achieving functional verification. A typical verification effort is centered around a stimuli generator which produces a massive amount of test cases that are simulated on the verified design. Bugs are then identified when the design behaves incorrectly. (in some cases this process is complemented by some amount of formal verification).

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References

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Authors and Affiliations

  1. IBM Haifa Research Lab, Haifa University Campus, Haifa, 31905, Israel

    Yehuda Naveh & Roy Emek

Authors
  1. Yehuda Naveh
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  2. Roy Emek
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Editor information

Editors and Affiliations

  1. Cheriton School of Computer Science, University of Waterloo, N2L 3G1, Waterloo, Ontario, Canada

    Peter van Beek

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© 2005 Springer-Verlag Berlin Heidelberg

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Naveh, Y., Emek, R. (2005). Random Stimuli Generation for Functional Hardware Verification as a CP Application. In: van Beek, P. (eds) Principles and Practice of Constraint Programming - CP 2005. CP 2005. Lecture Notes in Computer Science, vol 3709. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11564751_120

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  • DOI: https://doi.org/10.1007/11564751_120

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29238-8

  • Online ISBN: 978-3-540-32050-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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