Skip to main content

Architectural Enhancements for Color Image and Video Processing on Embedded Systems

  • Conference paper
Advances in Computer Systems Architecture (ACSAC 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3740))

Included in the following conference series:

Abstract

Application-specific extensions of a processor provide an efficient mechanism to meet the growing performance demands of multimedia applications. This paper presents a color-aware instruction set extension (CAX) for embedded multimedia systems that supports vector processing of color image sequences. CAX supports parallel operations on two-packed 16-bit (6:5:5) YCbCr (luminance-chrominance) data in a 32-bit datapath processor, providing greater concurrency and efficiency for color image and video processing. Unlike typical multimedia extensions (e.g., MMX, VIS, and MDMX), CAX harnesses parallelism within the human perceptual YCbCr space, rather than depending solely on generic subword parallelism. Experimental results on an identically configured, dynamically scheduled 4-way superscalar processor indicate that CAX outperforms MDMX (a representative MIPS multimedia extension) in terms of speedup (3.9× with CAX, but only 2.1× with MDMX over the baseline performance) and energy reduction (68% to 83% reduction with CAX, but only 39% to 69% reduction with MDMX over the baseline). More exhaustive simulations are conducted to provide an in-depth analysis of CAX on machines with varying issue widths, ranging from 1 to 16 instructions per cycle. The impact of the CAX plus loop unrolling is also presented.

This work was performed by author at the Georgia Institute of Technology (Atlanta, GA).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. Austin, T., Burger, D.: The SimpleScalar Tool Set. Version 2.0. TR-1342, Computer Sciences department, University of Wisconsin, Madison

    Google Scholar 

  2. Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc. of the IEEE Intl. Symp. on Computer Architecture, pp. 83–94 (2000)

    Google Scholar 

  3. Dongarra, J.J., Hinds, A.R.: Unrolling loops in Fortran. Software-Practice and Experience 9(3), 219–226 (1979)

    Article  MATH  Google Scholar 

  4. Gonzalez, R.C., Woods, R.E.: Digital Image Processing, 2nd edn. Prentice-Hall, Englewood Cliffs (2002)

    Google Scholar 

  5. Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Francisco (2003)

    Google Scholar 

  6. Kim, J.: Architectural enhancements for color image and video processing on embedded systems. PhD dissertation, Georgia Inst. of Technology (2005)

    Google Scholar 

  7. Kim, J., Wills, D.S.: Evaluating a 16-bit YCbCr (6:5:5) color representation for low memory, embedded video processing. In: Proc. of the IEEE Intl. Conf. on Consumer Electronics, pp. 181–182 (2005)

    Google Scholar 

  8. Koschan, A.: A comparative study on color edge detection. In: Proc. of the 2nd Asian Conference on Computer Vision, vol. III, pp. 574–578 (1995)

    Google Scholar 

  9. MIPS extension for digital media with 3D. Technical Report, MIPS technologies, Inc. (1997), http://www.mips.com

  10. MMXTM Technology Technical Overview, http://www.x86.org/intel.doc/mmxmanuals.htm

  11. Nguyen, H., John, L.: Exploiting SIMD parallelism in DSP and multimedia algorithms using the AltiVec technology. In: Proc. Intl. Conf. on Supercomputer, pp. 11–20 (1999)

    Google Scholar 

  12. Peleg, A., Weiser, U.: MMX technology extension to the Intel architecture. IEEE Micro 16(4), 42–50 (1996)

    Article  Google Scholar 

  13. Slingerland, N., Smith, A.J.: Measuring the performance of multimedia instruction sets. IEEE Trans. on Computers 51(11), 1317–1332 (2002)

    Article  MathSciNet  Google Scholar 

  14. Suh, J., Prasanna, V.K.: An efficient algorithm for out-of-core matrix transposition. IEEE Trans. on Computers 51(4), 420–438 (2002)

    Article  MathSciNet  Google Scholar 

  15. Tiwari, V., Malik, S., Wolfe, A.: Compilation techniques for low energy: An overview. In: Proc. of the IEEE Intl. Symp. on Low Power Electron, pp. 38–39 (1994)

    Google Scholar 

  16. Tremblay, M., O’Connor, J.M., Narayanan, V., He, L.: VIS speeds new media processing. IEEE Micro 16(4), 10–20 (1996)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Kim, J., Wills, D.S., Wills, L.M. (2005). Architectural Enhancements for Color Image and Video Processing on Embedded Systems. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_10

Download citation

  • DOI: https://doi.org/10.1007/11572961_10

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29643-0

  • Online ISBN: 978-3-540-32108-8

  • eBook Packages: Computer ScienceComputer Science (R0)

Publish with us

Policies and ethics