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The Challenges of Massive On-Chip Concurrency

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Advances in Computer Systems Architecture (ACSAC 2005)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 3740))

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Abstract

Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This growth poses major problems (and provides opportunities) for computer architecture in this time frame. The problems arise from current architectural approaches, which do not scale well and have used clock speed rather than concurrency to increase performance. This, in turn, causes excessive power dissipation and circuit complexity. This paper takes a long-range position on the future of chip multiprocessors, both from the micro-architecture perspective, as well as from a systems perspective. Concurrency will come from many levels, with instruction and loop-level concurrency managed at the micro-architecture and higher levels by the system. Chip-level multiprocessors exploiting massive concurrency we term Microgrids. The directions proposed in this paper provide micro-architectural concurrency with full forward compatibility over orders of magnitude of scaling and also the management of on-chip resources (processors etc.) so as to autonomously configure a system for a variety of goals (e.g. low power, high performance, etc.).

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Author information

Authors and Affiliations

  1. Computer Systems Architecture Group, Instituut voor informatica, Universiteit van Amsterdam,  

    Kostas Bousias & Chris Jesshope

Authors
  1. Kostas Bousias
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  2. Chris Jesshope
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Editor information

Editors and Affiliations

  1. Centre for High Performance Embedded Systems, School of Computer Engineering, Nanyang Technological University, 639798, Singapore

    Thambipillai Srikanthan

  2. National ICT, Australia

    Jingling Xue

  3. Centre for High Performance Embedded Systems, Nanyang Technological University, 639798, Singapore

    Chip-Hong Chang

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© 2005 Springer-Verlag Berlin Heidelberg

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Bousias, K., Jesshope, C. (2005). The Challenges of Massive On-Chip Concurrency. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_14

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  • DOI: https://doi.org/10.1007/11572961_14

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-29643-0

  • Online ISBN: 978-3-540-32108-8

  • eBook Packages: Computer ScienceComputer Science (R0)

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