Abstract
This paper presents a novel methodology for instruction set customization of RISPs (Reconfigurable Instruction Set Processors) using morphable structures. A morphable structure consists of a group of hardware operators chained together to implement a restricted set of custom instructions. These structures are implemented on the reconfigurable fabric, and the operators are enabled/disabled on demand. The utilization of a predefined set of morphable structures for instruction set customization dispenses the need for hardware synthesis in design exploration, and avoids run-time reconfiguration while minimizing the reconfigurable area. We will describe the two stages of the methodology for constructing the morphable structures, namely template generation and identification of a maximal unique pattern set from the templates. Our preliminary studies show that 23 predefined morphable structures can sufficiently cater to any application in a set of eight MiBench benchmark applications. In addition, to achieve near-optimal performance, the maximum required number of morphable structures for an application is only 8.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Dutt, N., Choi, K.: Configurable Processors for Embedded Computing. Computer 36(1), 120–123 (2003)
Henkel, J.: Closing the SoC Design Gap. IEEE Computer 36(9), 119–121 (2003)
Xtensa Microprocessor, http://www.tensilica.com
ARCtangent Processor, http://www.arc.com
Barat, F., Lauwereins, R., Deconinck, G.: Reconfigurable Instruction Set Processors from a Hardware/Software Perspective. IEEE Transactions on Software Engineering 28(9), 847–862 (2002)
Atasu, K., Pozzi, L., Ienne, P.: Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. In: Proceedings of the 40th IEEE/ACM Design Automation Conference, pp. 256–261 (2003)
Ohlrich, M., Ebeling, C., Ginting, E., Sather, L.: SubGemini: Identifying Subcircuits Using a Fast Subgraph Isomorphism Algorithm. In: Proceedings of the 30th ACM/IEEE Design Automation Conference, pp. 31–37 (1993)
Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: IEEE International Workshop on Workload Characterization, pp. 3–14 (2001)
Wirthlin, M.J., Hutchings, B.L.: A Dynamic Instruction Set Computer. In: Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 99–107 (1995)
Kastrup, B., Bink, A., Hoogerbrugge, J.: ConCISe: A Compiler-Driven CPLD-based Instruction Set Accelerator. In: Proceedings.of the 7th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 92–101 (1999)
Flaherty, N.: On the Chip or On the Fly. IEE Review 50(9), 48–51 (2004)
Xilinx Platform FPGAs, http://www.xilinx.com
Altera Nios Soft Core Embedded Processor, http://www.altera.com
Kastner, R., Kaplan, A., Memik, S.O., Bozorgzadeh, E.: Instruction Generation for Hybrid Reconfigurable Systems. ACM Transactions on Design Automation of Embedded Systems 7(4), 605–627 (2002)
Clark, N., Zhong, H., Mahlke, S.: Processor Acceleration Through Automated Instruction Set Customization. In: Proceedings of the 36th IEEE/ACM International Symposium on Microarchitecture (2003)
Biswas, P., Choudhary, V., Atasu, K., Pozzi, L., Ienne, P., Dutt, N.: Introduction of Local Memory Elements in Instruction Set Extensions. In: Proceedings of the 41st Annual IEEE/ACM Design Automation Conference, pp. 729–734 (2004)
Cong, J., Fan, Y., Han, G., Zhang, Z.: Application-Specific Instruction Generation for Configurable Processor Architectures. In: Proceedings of the 12th International Symposium on Field Programmable Gate Arrays, pp. 183–189 (2004)
Sassone, P.G., Wills, D.S.: On the Extraction and Analysis of Prevalent Dataflow Patterns. In: Proceedings of the Workshop on Workload Characterization (2004)
Spadini, F., Fertig, M., Patel, S.: Charaterization of Repeating Dynamic Code Fragments, Technical Report CRHC-02-09, University of Illinois, Urbana-Champaign (2002)
Trimaran: An Infrastructure for Research in Instruction-Level Parallelism, http://www.trimaran.org
Yu, P., Mitra, T.: Characterizing Embedded Applications for Instruction-Set Extensible Processors. In: Proceedings of the 41st IEEE/ACM on Design Automation Conference, pp. 723–728 (2004)
Cordella, L.P., Foggia, P., Sansone, C., Vento, M.: Performance Evaluation of the VF Graph Matching Algorithm. In: International Conference on Image Analysis and Processing, pp. 1172–1177 (1999)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lam, SK., Yun, D., Srikanthan, T. (2005). Morphable Structures for Reconfigurable Instruction Set Processors. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_36
Download citation
DOI: https://doi.org/10.1007/11572961_36
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29643-0
Online ISBN: 978-3-540-32108-8
eBook Packages: Computer ScienceComputer Science (R0)