Abstract
It may be impractical to have TAM for test usage only in NoC because it causes enormous hardware overhead. Therefore, the reuse of on-chip networks for TAM is very attractive and logical. In network-based TAM, an effective test scheduling for built-in cores is also important to minimize the total test time. In this paper, we propose a new efficient test scheduling algorithm for NoC based on the reuse of on-chip networks. Experimental results using some ITC’02 benchmark circuits show the proposed algorithm can reduce the test time by about 5 – 20% compared to previous methods. Consequently, the proposed algorithm can be widely used due to its feasibility and practicality.
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© 2005 Springer-Verlag Berlin Heidelberg
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Ahn, JH., Moon, B.I., Kang, S. (2005). A Practical Test Scheduling Using Network-Based TAM in Network on Chip Architecture. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_50
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DOI: https://doi.org/10.1007/11572961_50
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-29643-0
Online ISBN: 978-3-540-32108-8
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