Abstract
The design of an efficient reusable IP based Extended JPEG encoder is presented in this paper. This encoder uses user-defined quantization and Huffman tables that can be reconfigured at run-time. It has a modularized and pipelined architecture with distributed control for each block. A simple interface makes integration of the modules in various systems simple and straightforward. The design when targeted on FPGA operated at speed of up to 90MHz and when mapped on 0.25μm CMOS process the design can operate at speeds over 450MHz, which is faster than any of the similar JPEG encoder designs reported.
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© 2005 Springer-Verlag Berlin Heidelberg
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Mujahid, F.A., Jung, EG., Har, DS., Hong, JH., Lim, HJ. (2005). High Speed JPEG Coder Based on Modularized and Pipelined Architecture with Distributed Control. In: Ho, YS., Kim, H.J. (eds) Advances in Multimedia Information Processing - PCM 2005. PCM 2005. Lecture Notes in Computer Science, vol 3767. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11581772_41
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DOI: https://doi.org/10.1007/11581772_41
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30027-4
Online ISBN: 978-3-540-32130-9
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