Abstract
The future System-on-Chip (SoC) design will integrate a variety of intellectual properties (IPs). The clocked bus architectures to interconnect the IPs under the deep submicron technology suffer from problems related with the clock distribution, the synchronization of all IPs, the long arbitration delay and the limited bandwidth. These problems can be resolved by adopting new interconnection architecture such as Network-on-Chip (NoC) or the asynchronous design method. In this paper, a design methodology for an asynchronous switch based on butterfly fat-tree topology is proposed. The wormhole switching technique is adopted to reduce the latency and the buffer size. The source-based routing mechanism and the output buffering strategy are used to reduce the switch design cost and increase the performance.
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References
International Technology Roadmap For Semiconductors 2001 edn., http://public.itrs.net/Files/2001ITRS/Home.htm
Dehon, A.: Compact, Multilayer Layout for Butterfly Fat-Tree. In: Twelfth Annual ACM Symposium on Parallel Algorithms and Architectures, SPAA 2000, July 9-12, pp. 206–215 (2000)
Guerrier, P., Greiner, A.: A generic architecture for on-chip packet-switched interconnections. In: Proceedings of Design Automation and Test Conference in Europe, pp. 250–256 (2000)
Greenberg, R.I., Guan, L.: An improved analytical model for wormhole routed networks with application to butterfly fat-trees. In: Proceedings of the 1997 International Conference on Parallel Processing, pp. 44–48 (1997)
Leiserson, C.E.: Fat Trees: Universal networks for hardware efficient supercomputing. IEEE Transactions on Computers C-34(10), 892–901 (1985)
Duato, J., Yalamanchile, S.: Interconnection Networks: An Engineering Approach, pp. 43–78. IEEE Computer Society, Los Alamitos (1997)
Furber, S.B., Day, P.: Four-Phase Micropipeline Latch Control Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 4(2) (June1996)
Xu, J.: Asynchronous interconnection and interfacing of intellectual property cores in the design of systems-on-chip. Ph.D. thesis, South Bank University (July 2002)
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© 2005 Springer-Verlag Berlin Heidelberg
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Kang, MC., Jung, EG., Har, DS. (2005). Design of an Asynchronous Switch Based on Butterfly Fat-Tree for Network-on-Chip Applications. In: Ho, YS., Kim, HJ. (eds) Advances in Multimedia Information Processing - PCM 2005. PCM 2005. Lecture Notes in Computer Science, vol 3768. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11582267_47
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DOI: https://doi.org/10.1007/11582267_47
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30040-3
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