Abstract
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Montanaro, J., et al.: A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. Digital Technical Journal (1), 49–62 (January 1997)
Geiger, M.J., McKee, S.A., Tyson, G.S.: Drowsy Region-Based Caches: Minimizing Both Dynamic and Static Power Dissipation. In: Proc. ACM International Conference on Computing Frontiers, May 2005, pp. 378–384 (2005)
Lee, H.S., Tyson, G.S.: Region-Based Caching: An Energy-Delay Efficient Memory Architecture for Embedded Processors. In: Proc. ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, November 2000, pp. 120–127 (2000)
Lee, H.S.: Improving Energy and Performance of Data Cache Architectures by Exploiting Memory Reference Characteristics. Doctoral thesis, The University of Michigan (2001)
Flautner, K., Kim, N.S., Martin, S., Blaauw, D., Mudge, T.: Drowsy Caches: Simple Techniques for Reducing Leakage Power. In: Proc. 29th IEEE/ACM International Symposium on Computer Architecture, May 2002, pp. 147–157 (2002)
Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Drowsy Instruction Caches: Leakage Power Reduction using Dynamic Voltage Scaling and Cache Sub-bank Prediction. In: 35th IEEE/ACM International Symposium on Microarchitecure, November 2002, pp. 219–230 (2002)
Kim, N.S., Flautner, K., Blaauw, D., Mudge, T.: Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power. IEEE Transactions on VLSI 12(2), 167–184 (2004)
Guthaus, M.R., Ringenberg, J., Ernst, D., Austin, T., Mudge, T., Brown, R.: MiBench: A Free, Commercially Representative Embedded Benchmark Suite. In: Proc. 4 th IEEE Workshop on Workload Characterization, December 2001, pp. 3–14 (2001)
Ghose, K., Kamble, M.B.: Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers and Bit-Line Segmentation. In: Proc. ACM/IEEE International Symposium on Low Power Electronics and Design, August 1999, pp. 70–75 (1999)
Su, C.-L., Despain, A.M.: Cache Designs for Energy Efficiency. In: Proc. 28th Hawaii International Conference on System Sciences, January 1995, pp. 306–315 (1995)
Kin, J., Gupta, M., Mangione-Smith, W.H.: Filtering Memory References to Increase Energy Efficiency. IEEE Transactions on Computers 49(1), 1–15 (2000)
Albonesi, D.H.: Selective Cache Ways: On-Demand Cache Resource Allocation. In: 32nd IEEE/ACM International Symposium on Microarchitecture, November 1999, pp. 248–259 (1999)
Yang, S.-H., Powell, M., Falsafi, B., Vijaykumar, T.N.: Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Eelay. In: Proc. 8th International Symposium on High-Performance Computer Architecture, February 2002, pp. 147–158 (2002)
Yang, S.-H., Powell, M.D., Falsafi, B., Roy, K., Vijaykumar, T.N.: An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches. In: Proc. 7th International Symposium on High-Performance Computer Architecture, January 2001, pp. 147–158 (2001)
Sugumar, R.A., Abraham, S.G.: Efficient Simulation of Multiple Cache Configurations using Binomial Trees. Technical Report CSE-TR-111-91, CSE Division, University of Michigan (1991)
Belady, L.A.: A Study of Replacement Algorithms for a Virtual-Storage Computer. IBM Systems Journal 5(2), 78–101 (1966)
Austin, T.: SimpleScalar 4.0 Release Note, http://www.simplescalar.com/
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. 27th IEEE/ACM International Symposium on Computer Architecture, June 2000, pp. 83–94 (2000)
Zhang, Y., Parikh, D., Sankaranarayanan, K., Skadron, K., Stan, M.: HotLeakage: A Temperature-Aware Model of Subthreshold and Gate Leakage for Architects. Technical Report CS-2003-05, University of Virginia Department of Computer Science (March 2003)
Parikh, D., Zhang, Y., Sankaranarayanan, K., Skadron, K., Stan, M.: Comparison of State-Preserving vs. Non-State-Preserving Leakage Control in Caches. In: Proc. 2nd Workshop on Duplicating, Deconstructing, and Debunking, June 2003, pp. 14–24 (2003)
Gonzales, R., Horowitz, M.: Energy Dissipation In General Purpose Microprocessors. IEEE Journal of Solid State Circuits 31(9), 1277–1284 (1996)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Geiger, M.J., McKee, S.A., Tyson, G.S. (2005). Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. In: Conte, T., Navarro, N., Hwu, Wm.W., Valero, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2005. Lecture Notes in Computer Science, vol 3793. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11587514_8
Download citation
DOI: https://doi.org/10.1007/11587514_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30317-6
Online ISBN: 978-3-540-32272-6
eBook Packages: Computer ScienceComputer Science (R0)