Abstract
Increasingly tight energy design goals require processor architects to rethink the organizational structure of microarchitectural resources. In this paper, we examine a new multilateral cache organization that replaces a conventional data cache with a set of smaller region caches that significantly reduces energy consumption with little performance impact. This is achieved by tailoring the cache resources to the specific reference characteristics of each application.
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Geiger, M.J., McKee, S.A., Tyson, G.S. (2005). Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation. In: Conte, T., Navarro, N., Hwu, Wm.W., Valero, M., Ungerer, T. (eds) High Performance Embedded Architectures and Compilers. HiPEAC 2005. Lecture Notes in Computer Science, vol 3793. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11587514_8
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DOI: https://doi.org/10.1007/11587514_8
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30317-6
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