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Toward Real Time Fractal Image Compression Using Graphics Hardware

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Advances in Visual Computing (ISVC 2005)

Part of the book series: Lecture Notes in Computer Science ((LNIP,volume 3804))

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Abstract

In this paper, we present a parallel fractal image compression using the programmable graphics hardware. The main problem of fractal compression is the very high computing time needed to encode images. Our implementation exploits SIMD architecture and inherent parallelism of recently graphic boards to speed-up baseline approach of fractal encoding. The results we present are achieved on cheap and widely available graphics boards.

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Author information

Authors and Affiliations

  1. ISISLab – Dipartimento di Informatica ed Appl. “R.M. Capocelli”, Università degli Studi di Salerno, 84081, Baronissi, Italy

    Ugo Erra

Authors
  1. Ugo Erra
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Editor information

Editors and Affiliations

  1. Department of Computer Science and Engineering, University of Nevada, Reno, USA

    George Bebis

  2. NASA Ames Research Center, Moffett Field, CA, USA

    Richard Boyle

  3. Desert Research Institute, Reno, NV, USA

    Darko Koracin

  4. Lawrence Berkeley National Laboratory, Berkeley, CA, USA

    Bahram Parvin

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© 2005 Springer-Verlag Berlin Heidelberg

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Erra, U. (2005). Toward Real Time Fractal Image Compression Using Graphics Hardware. In: Bebis, G., Boyle, R., Koracin, D., Parvin, B. (eds) Advances in Visual Computing. ISVC 2005. Lecture Notes in Computer Science, vol 3804. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11595755_92

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  • DOI: https://doi.org/10.1007/11595755_92

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-30750-1

  • Online ISBN: 978-3-540-32284-9

  • eBook Packages: Computer ScienceComputer Science (R0)

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