Abstract
Power leakage constitutes an increasing fraction of the total power consumption in modern semiconductor technologies. Recent research efforts also indicate architecture, compiler, and software participations can help reduce the switching activities (also known as dynamic power) on microprocessors. This raises interests on the issues to employ architecture and compiler efforts to reduce leakage power (also known as static power) on microprocessors. In this paper, we investigate the compiler analysis techniques related to reducing leakage power. The architecture model in our design is a system with an instruction set to support the control of power gating in the component levels. Our compiler gives an analysis framework to utilize the instruction to reduce the leakage power. We present a data flow analysis framework to estimate the component activities at fixed points of programs with the consideration of pipelines of architectures. We also give the equation for the compiler to decide if the employment of the power gating instructions on given program blocks will benefit the total energy reductions. As the duration of power gating on components on given program routines is related to program branches, we propose a set of scheduling policy include Basic_Blk_Sched, MIN_Path_Sched, and AVG_Path_Sched mechanisms and evaluate the effectiveness of those schemes. Our experiment is done by incorporating our compiler analysis and scheduling policy into SUIF compiler tools [32] and by simulating the energy consumptions on Wattch toolkits [6]. Experimental results show our mechanisms are effective in reducing leakage powers on microprocessors.
The work was supported in part by NSC-90-2218-E-007-042, NSC-90-2213-E-007-074, NSC-90-2213-E-007-075, MOE research excellent project under grant no. 89-E-FA04-1-4, and MOEA research project under grant no. 91-EC-17-A-03-S1-0002 of Taiwan.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Aburto, A.: Collections of common benchmarks of FAQ of comp.benchmarks USENET newsgroup, ftp site: http://ftp.nosc.mail/pub/aburto
Aho, A., Sethi, R., Ullman, J.: Compilers Principles, Techniques, and Tools. Addison- Wesley, London (1985)
Alidina, M., Monteiro, J., Devadas, S., Ghosh, A., Papaefthymiou, M.: Precomputation-Based Sequential Logic Optimization for Low Power. In: Proc. of ICCAD 1994, pp. 74–81 (1994)
Benini, L., De Micheli, G.: State Assignment for Low Power Dissipation. IEEE Journal of Solid State Circuits 30(3), 258–268 (1995)
Bellas, N., Hajj, I.N., Polychronopoulos, C.D.: Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 317–326 (June 2000)
Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a Framework for Architectural- Level Power Analysis and Optimizations. In: Proc. 27th. International Symposium on Computer Architecture, June 2000, pp. 83–94 (2000)
Burger, D., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0. Computer Architecture News, 13–25 (June 1997)
Butts, J.A., Sohi, G.S.: A Static Power Model for Architects. In: Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, December 2000, pp. 191–201 (2000)
Chang, R.G., Chuang, T.R., Lee, J.-K.: Efficient Support of Parallel Sparse Computation for Array Intrinsic Functions of Fortran 90. In: ACM International Conference on Supercomputing, Melbourne, Australia, July 13-17 (1998)
Chang, R.-G., Li, J.-S., Chuang, T.-R., Lee, J.K.: Probabilistic inference schemes for sparsity structures of Fortran 90 array intrinsics. In: International Conference on Parallel Processing, Spain (September 2001)
Chandrakasan, A.P., Sheng, S., Brodersen, R.W.: Low-Power CMOS Digital Design. IEEE Journal of Solid-State Circuits 27(4), 473–484 (1992)
Chang, J.-M., Pedram, M.: Register Allocation and Binding for Low Power. In: Proceedings of Design Automaton Conference, San Francisco, USA (June 1995)
Compaq Computer Corporation, Alpha 21264 Microprocessor Hardware Reference Manual, EC-RJRZA-TE (July 1999)
De, V., Borkar, S.: Technology and design challenges for low power and high performance. In: Proc. of Int. Symp. Low Power Electronics and Design, pp. 163–168 (1999)
Hachtel, G., Hermida, M., Pardo, A., Poncino, M., Somenzi, F.: Re-Encoding Sequential Circuits to Reduce Power Dissipation. In: Proc. of ICCAD 1994, pp. 70–73 (1994)
Hadjiyiannis, G., Hanono, S., Devadas, S.: ISDL: An Instruction Set Description Language for Retargetability. In: Design Automation Conference (June 1997)
Hwang, Y.-S., Chen, P.-S., Lee, J.-K., Ju, R.: Probabilistic Points-to Analysis. In: Dietz, H.G. (ed.) LCPC 2001. LNCS, vol. 2624. Springer, Heidelberg (2003)
Hwang, G.-H., Lee, J.K., Ju, R.D.-C.: A Function-Composition Approach to Synthesize Fortran 90 Array Operations. Journal of Parallel and Distributed Computing 54, 1–47 (1998)
Hong, I., Dirovski, D., et al.: Power Optimization of Variable Voltage Core- Based Systems. In: Proc. of 35th DAC, pp. 176–181 (1998)
Horowitz, M., Indermaur, T., Gonzalez, R.: Low-Power Digital Design. In: Proceedings of the 1994 IEEE Symposium on Low Power Electronics, pp. 8–11 (1994)
Intel corporation, Pentium III Processor for the SC242 at 450 MHz to 1.13 GHz Datasheet, pp. 26–30
Kao, J.T., Chandrakasan, A.P.: Dual-threshold voltage techniques for lowpower digital circuits. IEEE Journal of Solid-state circuits 35(7), 1009–1018 (2000)
Kaxiras, S., Hu, Z., Martonosi, M.: Cache Decay: Exploiting Generational Behavior to Reduce Cache Leakage Power. In: Proc. of the Int’l Symposium on Computer Architecture, pp. 240–251 (2001)
Lee, C., Lee, J.K., Hwang, T., Tsai, S.-C.: Compiler Optimization on Instruction Scheduling for Low Power. In: Proceedings of the 13th International Symposium on Systems Synthesis, September 2000, pp. 55–60 (2000)
Lee, M.T.-C., Tiwari, V., Malik, S., Fujita, M.: Power Analysis andMinimization Techniques for Embedded DSP Software. IEEE Transactions on VLSI Systems 5(1), 123–133 (1997)
Powell, M.D., Yang, S.-H., Falsa, B., Roy, K., Vijaykumar, T.N.: Gated- Vdd: a Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. In: ACM/IEEE International Symposium on Low Power Electronics and Design, ISLPED (2000)
Prasad, S.C., Roy, K.: Circuit Activity Driven Multilevel Logic Optimization for Low Power Reliable Operation. In: Proceedings of the EDAC 1993 EURO-ASIC, February 1993, pp. 368–372 (1993)
Rele, S., Pande, S., Onder, S., Gupta, R.: Optimizing Static Power Dissipation by Functional Units in Superscalar Processors. In: Horspool, R.N. (ed.) CC 2002. LNCS, vol. 2304, p. 261. Springer, Heidelberg (2002)
Roy, K., Prasad, S.C.: SYCLOP: Synthesis of CMOS Logic for Low Power Applications. In: Proceedings of the ICCD, pp. 464–467 (1992)
Roy, K.: Leakage Power reduction in Low-Voltage CMOS Designs. In: IEEE International Conference on Circuits and Systems, vol. 2, pp. 167–173 (1998)
Smith, M.D.: The SUIF Machine Library. In: Division of of Engineering and Applied Science. Harvard University, Cambridge (1998)
Stanford Compiler Group, The SUIF Library, Stanford Compiler Group, Stanford (March 1995)
Su, C.-L., Despain, A.M.: Cache Designs for Energy Efficiency. In: Proceedings of the 28th Annual Hawaii International Conference on System Sciences, pp. 306–315 (1995)
Tiwari, V., Donnelly, R., Malik, S., Gonzalez, R.: Dynamic Power Management for Microprocessors: A Case Study. In: Proceedings of the 10th International Conference on VLSI Design, pp. 185–192 (1997)
Tiwari, V., Singh, D., Rajgopal, S., Mehta, G., Patel, R., Baez, F.: Reducing Power in High-Performance Microprocessors. In: Proceedings of the Design Automaton Conference, pp. 732–737 (1998)
Thompson, S., Packan, P., Bohr, M.: MOS Scaling: Transistor Challenges for the 21st Century. Portland Technology Development, Intel. Corp. Intel. Technology Journal (Q3 1998)
Tsui, C.Y., Pedram, M., Despain, A.M.: Technology Decomposition and Mapping Targeting Low Power Dissipation. In: Proc. of 30th Design Automaton Conf., 68–73 (June 1993)
Wu, J.-Z., Lee, J.-K.: A bytecode optimizer to engineer bytecodes for performances. In: Midkiff, S.P., Moreira, J.E., Gupta, M., Chatterjee, S., Ferrante, J., Prins, J.F., Pugh, B., Tseng, C.-W. (eds.) LCPC 2000. LNCS, vol. 2017, p. 377. Springer, Heidelberg (2001)
You, Y.-P., Lee, C.-R., Lee, J.-K., Shih, W.-K.: Rea-Time Task Scheduling for Dynamically Variable Voltage Processors. In: IEEE workshop on Power Management for Real-Time and Embedded Systems (May 2001)
Zhang, W., Vijaykrishnan, N., Kandemir, M., Irwin, M.J., Duarte, D., Tsai, Y.: Exploiting VLIW Schedule Slacks for Dynamic and Leakage Energy Reduction. In: Proceedings of the Thirty-Fourth Annual International Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001, pp. 102–113 (2001)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
You, YP., Lee, C., Lee, J.K. (2005). Compiler Analysis and Supports for Leakage Power Reduction on Microprocessors. In: Pugh, B., Tseng, CW. (eds) Languages and Compilers for Parallel Computing. LCPC 2002. Lecture Notes in Computer Science, vol 2481. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11596110_4
Download citation
DOI: https://doi.org/10.1007/11596110_4
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-30781-5
Online ISBN: 978-3-540-31612-1
eBook Packages: Computer ScienceComputer Science (R0)